Stefan Holst
f863b70457
use float32 for delays, more robust node-port name splitting
19 hours ago
stefan
bd23dfb016
get a techlib by name
1 week ago
stefan
d3d06722c1
faster mv xor and new merge fct
2 weeks ago
stefan
1f984c9bd9
faster fanout generator function
2 weeks ago
stefan
0c8a2b7746
add return type
2 weeks ago
stefan
f66953f2d3
fix sim model gen for undriven outputs
2 weeks ago
stefan
7203145a1d
better docs and repr
2 weeks ago
stefan
32e0766d41
s_len param for vcd
2 weeks ago
stefan
9570161744
fix half adder
2 weeks ago
stefan
a594e2fb9a
annotation and repr
2 weeks ago
stefan
1bc9dc0e9d
bench parsing docs
3 weeks ago
Stefan Holst
c5bdeb4a68
add type annotation
3 weeks ago
Stefan Holst
67db64611b
fix cuda launch expecting pure ints for grid spec
3 weeks ago
stefan
7a9ed1e536
vcd improvements
3 weeks ago
stefan
fcd9b78c24
rm test.py
3 weeks ago
stefan
f975765bbb
first version of a vcd parser
3 weeks ago
stefan
3cb1b2bc86
first version of a vcd parser
3 weeks ago
stefan
c4aecbd6c9
skywater 130nm tech library
1 month ago
stefan
25ff1fb2dc
fixups for empty standard cells
1 month ago
Stefan Holst
f0b55eed27
version bump
6 months ago
Stefan Holst
3700ae9b33
need 3.12 for generic types
6 months ago
Stefan Holst
df695e0aa1
for release 0.0.6
...
- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API)
- sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic
- Circuit: dot output fix and better style, fixed equivalence check of lines and nodes.
- Techlib: Added KYUPY library with supported simulation primitives for debug and testing
- tests: fixed and added more for better coverage
- more type annotations
- updated project config and dependencies for better uv experience, newer lark, newer numpy
6 months ago
Stefan Holst
a28128830d
beginning simple always block parsing in verilog
6 months ago
Stefan Holst
20cf441abb
add doc gen dependencies
6 months ago
Stefan Holst
5ac21edbb1
migrate readme to markdown
6 months ago
Stefan Holst
f0d74777af
add dff to techlib
6 months ago
Stefan Holst
3848665533
ignore more generated python files
6 months ago
Stefan Holst
541cccd756
fix sim model for PO that also drive further logic
6 months ago
Stefan Holst
fed66f85cb
fix oob in test
6 months ago
Stefan Holst
2eb10f83b0
add pytest dev dependency
6 months ago
Stefan Holst
dd4e5c861a
fix sim model generation for circuits with dangling nodes
6 months ago
Stefan Holst
9cebbcce8f
support for storing responses separately
7 months ago
stefan
31434cfd51
4v sim, fixed 6v sim, better testing
7 months ago
stefan
ce94210b52
adding more types
7 months ago
Stefan Holst
09420fd72c
new logic sim interface prototype, simprim lib and test
7 months ago
Stefan Holst
5bcc1c1d77
new synthetic techlib with kyupy simprims
7 months ago
Stefan Holst
df8a58f57b
generate proper simprims in bench parser
7 months ago
Stefan Holst
3dfd0cb60d
euivalence test, op format doc
7 months ago
Stefan Holst
21439e3595
circuit objects and nodes/lines of different circuits are not quivalent.
7 months ago
Stefan Holst
88a5c79161
dot fix and updated intro nb
7 months ago
Stefan Holst
9ca437fe47
fault injection for 4v sim, wave_sim test fix
7 months ago
Stefan Holst
0cdaf71963
fix for latest lark
7 months ago
Stefan Holst
75972d7bb2
numba config deprecated
7 months ago
Stefan Holst
469dc18aa9
lark dependency update
7 months ago
stefan
33addab141
fix output with newest numpy
7 months ago
Stefan Holst
674f3dea4a
Merge branch 'main' into devel
11 months ago
Stefan Holst
55d62ff354
sphinx config
11 months ago
Stefan Holst
e311b1098a
sphinx config
11 months ago
Stefan Holst
aea633ac8d
for release 0.0.5
...
* Techlib: fix NanGate variants
* Circuit: more visitor and manipulator utilities
* mv_transition: produce stable values when arguments are UNASSIGNED
* Verilog: better assign processing
* STIL parsing improvements
* SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching
* sim: use ALAP topo-sort
* logic_sim: improved fault injection, faster 6V sim
* wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor
* log: fix limiter
11 months ago
Stefan Holst
187d176cfd
partial ternary if support
12 months ago
