Tree: f17e461fdd

devel

main

v0.0.1

v0.0.2

v0.0.3

v0.0.4

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from 'f17e461fdd'

${ noResults }

Commit Graph

5 Commits (f17e461fdd2d78a622a1bc5885c68162a9e6f345)

Author	SHA1	Message	Date
stefan	1eb8d87884	faster logic sim, removing MVArray, BPArray	2 years ago
Stefan Holst	840b816804	Circuit pickle, STIL/SDF/techlib fixes, sdata ... - fix pin indices for various SC lib variants - SDF annotation improvements - STIL loading improvements - Support for per-simulation parameters in WaveSim - Circuit is now pickleable and comparable	2 years ago
Stefan Holst	864230b883	initial letch support, fix capture in logic sim	4 years ago
Stefan Holst	64e1de396f	New m-valued logic arrays, documentation, 0.0.2 ... - MVArray for multi-valued logic - BPArray for bit-parallel storage layout - Started documenting with Sphinx - Migrated simulators to new BPArray	4 years ago
Stefan Holst	7f035c1ac5	Migration to new logic value representation	4 years ago
Stefan Holst	7bcfbf502b	Documentation, cleanup, multi-valued logic	4 years ago
Stefan Holst	a77ac4a397	start designing new data structures for m-valued logic	4 years ago