5 Commits

Include renames

Author	SHA1	Message	Date
stefan	aea633ac8d	for release 0.0.5 ... * Techlib: fix NanGate variants * Circuit: more visitor and manipulator utilities * mv_transition: produce stable values when arguments are UNASSIGNED * Verilog: better assign processing * STIL parsing improvements * SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching * sim: use ALAP topo-sort * logic_sim: improved fault injection, faster 6V sim * wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor * log: fix limiter	2025-06-23 15:39:55 +09:00
Stefan Holst	9f9902c613	remove _static	2023-07-22 16:48:51 +09:00
Stefan Holst	351d809306	for release 0.0.4 ... - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements	2023-07-22 16:13:01 +09:00
Stefan Holst	c9445f2d79	Docs, __index__, fault injection and TechLib ... - Documentation improvements - Node and Line objects now provide __index__ - LogicSim cleanup and improvements (inject_cb, cycle, ...) - Introduce TechLib class to organize tech-specific info - More human-readable output - De-linting	2021-01-16 14:48:27 +09:00
Stefan Holst	64e1de396f	New m-valued logic arrays, documentation, 0.0.2 ... - MVArray for multi-valued logic - BPArray for bit-parallel storage layout - Started documenting with Sphinx - Migrated simulators to new BPArray	2020-12-21 20:44:23 +09:00