for release 0.0.4

- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements

docs/Makefile

@@ -1,3 +1,5 @@
+# pip install sphinx sphinx-rtd-theme
+#
 # Minimal makefile for Sphinx documentation
 #
 

docs/circuit.rst

@@ -0,0 +1,13 @@
+Circuit Graph - :mod:`kyupy.circuit`
+====================================
+
+.. automodule:: kyupy.circuit
+
+.. autoclass:: kyupy.circuit.Node
+   :members:
+
+.. autoclass:: kyupy.circuit.Line
+   :members:
+
+.. autoclass:: kyupy.circuit.Circuit
+   :members:

docs/conf.py

@@ -20,11 +20,11 @@ sys.path.insert(0, os.path.abspath('../src'))
 # -- Project information -----------------------------------------------------
 
 project = 'KyuPy'
-copyright = '2020-2021, Stefan Holst'
+copyright = '2020-2023, Stefan Holst'
 author = 'Stefan Holst'
 
 # The full version, including alpha/beta/rc tags
-release = '0.0.3'
+release = '0.0.4'
 
 
 # -- General configuration ---------------------------------------------------

docs/datastructures.rst

@@ -1,29 +0,0 @@
-Data Structures
-===============
-
-KyuPy provides two types of core data structures, one for gate-level circuits, and a few others for representing and storing logic data and signal values.
-The data structures are designed to work together nicely with numpy arrays.
-For example, all the nodes and connections in the circuit graph have consecutive integer indices that can be used to access ndarrays with associated data.
-Circuit graphs also define an ordering of inputs, outputs and other nodes to easily process test vector data and alike.
-
-Circuit Graph - :mod:`kyupy.circuit`
-------------------------------------
-
-.. automodule:: kyupy.circuit
-
-.. autoclass:: kyupy.circuit.Node
-   :members:
-
-.. autoclass:: kyupy.circuit.Line
-   :members:
-
-.. autoclass:: kyupy.circuit.Circuit
-   :members:
-
-Multi-Valued Logic - :mod:`kyupy.logic`
----------------------------------------
-
-.. automodule:: kyupy.logic
-   :members:
-
-

docs/index.rst

@@ -4,9 +4,11 @@ API Reference
 -------------
 
 .. toctree::
-   :maxdepth: 2
+   :maxdepth: 1
 
-   datastructures
+   circuit
+   logic
+   techlib
    parsers
    simulators
    miscellaneous

docs/logic.rst

@@ -0,0 +1,7 @@
+Multi-Valued Logic - :mod:`kyupy.logic`
+=======================================
+
+.. automodule:: kyupy.logic
+   :members:
+
+

docs/miscellaneous.rst

@@ -4,7 +4,3 @@ Miscellaneous
 .. automodule:: kyupy
    :members:
 
-.. automodule:: kyupy.techlib
-   :members:
-
-

docs/parsers.rst

@@ -40,3 +40,12 @@ Standard Delay Format - :mod:`kyupy.sdf`
 
 .. autoclass:: kyupy.sdf.DelayFile
    :members:
+
+Design Exchange Format - :mod:`kyupy.def_file`
+----------------------------------------------
+
+.. automodule:: kyupy.def_file
+   :members: parse, load
+
+.. autoclass:: kyupy.def_file.DefFile
+   :members:

docs/simulators.rst

@@ -1,6 +1,11 @@
 Simulators
 ==========
 
+KyuPy's simulators are optimized for cells with at most 4 inputs and 1 output.
+
+More complex cells must be mapped to simulation primitives first.
+
+
 Logic Simulation - :mod:`kyupy.logic_sim`
 -----------------------------------------
 

docs/techlib.rst

@@ -0,0 +1,7 @@
+Technology Libraries
+====================
+
+.. automodule:: kyupy.techlib
+   :members:
+
+