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248 Commits (aabef17eeac46508e36800d2ab62566a8902df78)
 

Author SHA1 Message Date
Stefan Holst aabef17eea parse sky130 def files
2 months ago
stefan f0c10633bf disconnect unused clk from dff to prevent spurious sanity check fails
2 months ago
stefan ed9b5c6cd6 fix sim scheduler for circuits with POs that are also used internally
2 months ago
stefan e19463d249 fix LogicSim for 2v, deterministic sim schedule, towards sub-sims for partitions
2 months ago
stefan 7a69ce9016 sort times
2 months ago
stefan f5af7ec3d9 typing and docs for interpret, mvarray
2 months ago
stefan 53309f9e59 simple incremental sim using dirty flags
3 months ago
stefan c90bc89522 construct input connected to output on passthrough connection
3 months ago
stefan bda89dc1b0 support for simple text-based pattern format
3 months ago
stefan 449bf9a031 more flexible progress logging
3 months ago
stefan df463826ae fix ffr
3 months ago
stefan aebdf9540d pin_name type annotations
3 months ago
stefan 9dc58f8c40 dev deps
3 months ago
stefan e8a9025c56 fix dot graph construction
3 months ago
stefan 8aa0f09254 logic_sim: better docs, deprecate LogicSim, move tests to newer classes
3 months ago
stefan 4f7e605819 use tlib functions to identify ffs and latches
3 months ago
stefan c1ea05555e fix verilog tests
3 months ago
stefan e7b5567d87 let SimOps refuse building broken sim models.
3 months ago
stefan 3a2cfb7788 techlib decides on cell type comb/dff/latch
3 months ago
Stefan Holst ca25942b27 better type annotation, always return list
3 months ago
Stefan Holst f863b70457 use float32 for delays, more robust node-port name splitting
3 months ago
stefan bd23dfb016 get a techlib by name
4 months ago
stefan d3d06722c1 faster mv xor and new merge fct
4 months ago
stefan 1f984c9bd9 faster fanout generator function
4 months ago
stefan 0c8a2b7746 add return type
4 months ago
stefan f66953f2d3 fix sim model gen for undriven outputs
4 months ago
stefan 7203145a1d better docs and repr
4 months ago
stefan 32e0766d41 s_len param for vcd
4 months ago
stefan 9570161744 fix half adder
4 months ago
stefan a594e2fb9a annotation and repr
4 months ago
stefan 1bc9dc0e9d bench parsing docs
4 months ago
Stefan Holst c5bdeb4a68 add type annotation
4 months ago
Stefan Holst 67db64611b fix cuda launch expecting pure ints for grid spec
4 months ago
stefan 7a9ed1e536 vcd improvements
4 months ago
stefan fcd9b78c24 rm test.py
4 months ago
stefan f975765bbb first version of a vcd parser
4 months ago
stefan 3cb1b2bc86 first version of a vcd parser
4 months ago
stefan c4aecbd6c9 skywater 130nm tech library
5 months ago
stefan 25ff1fb2dc fixups for empty standard cells
5 months ago
Stefan Holst f0b55eed27 version bump
10 months ago
Stefan Holst 3700ae9b33 need 3.12 for generic types
10 months ago
Stefan Holst df695e0aa1 for release 0.0.6
10 months ago
Stefan Holst a28128830d beginning simple always block parsing in verilog
10 months ago
Stefan Holst 20cf441abb add doc gen dependencies
10 months ago
Stefan Holst 5ac21edbb1 migrate readme to markdown
10 months ago
Stefan Holst f0d74777af add dff to techlib
10 months ago
Stefan Holst 3848665533 ignore more generated python files
10 months ago
Stefan Holst 541cccd756 fix sim model for PO that also drive further logic
10 months ago
Stefan Holst fed66f85cb fix oob in test
10 months ago
Stefan Holst 2eb10f83b0 add pytest dev dependency
10 months ago