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234 Commits (8aa0f092549b9a6b9ee2141b61e4d00b5dd24119)
 

Author SHA1 Message Date
stefan 8aa0f09254 logic_sim: better docs, deprecate LogicSim, move tests to newer classes
2 months ago
stefan 4f7e605819 use tlib functions to identify ffs and latches
2 months ago
stefan c1ea05555e fix verilog tests
2 months ago
stefan e7b5567d87 let SimOps refuse building broken sim models.
2 months ago
stefan 3a2cfb7788 techlib decides on cell type comb/dff/latch
2 months ago
Stefan Holst ca25942b27 better type annotation, always return list
2 months ago
Stefan Holst f863b70457 use float32 for delays, more robust node-port name splitting
3 months ago
stefan bd23dfb016 get a techlib by name
3 months ago
stefan d3d06722c1 faster mv xor and new merge fct
3 months ago
stefan 1f984c9bd9 faster fanout generator function
3 months ago
stefan 0c8a2b7746 add return type
3 months ago
stefan f66953f2d3 fix sim model gen for undriven outputs
3 months ago
stefan 7203145a1d better docs and repr
3 months ago
stefan 32e0766d41 s_len param for vcd
3 months ago
stefan 9570161744 fix half adder
3 months ago
stefan a594e2fb9a annotation and repr
3 months ago
stefan 1bc9dc0e9d bench parsing docs
3 months ago
Stefan Holst c5bdeb4a68 add type annotation
3 months ago
Stefan Holst 67db64611b fix cuda launch expecting pure ints for grid spec
3 months ago
stefan 7a9ed1e536 vcd improvements
3 months ago
stefan fcd9b78c24 rm test.py
4 months ago
stefan f975765bbb first version of a vcd parser
4 months ago
stefan 3cb1b2bc86 first version of a vcd parser
4 months ago
stefan c4aecbd6c9 skywater 130nm tech library
4 months ago
stefan 25ff1fb2dc fixups for empty standard cells
4 months ago
Stefan Holst f0b55eed27 version bump
9 months ago
Stefan Holst 3700ae9b33 need 3.12 for generic types
9 months ago
Stefan Holst df695e0aa1 for release 0.0.6
9 months ago
Stefan Holst a28128830d beginning simple always block parsing in verilog
9 months ago
Stefan Holst 20cf441abb add doc gen dependencies
9 months ago
Stefan Holst 5ac21edbb1 migrate readme to markdown
9 months ago
Stefan Holst f0d74777af add dff to techlib
9 months ago
Stefan Holst 3848665533 ignore more generated python files
9 months ago
Stefan Holst 541cccd756 fix sim model for PO that also drive further logic
9 months ago
Stefan Holst fed66f85cb fix oob in test
9 months ago
Stefan Holst 2eb10f83b0 add pytest dev dependency
9 months ago
Stefan Holst dd4e5c861a fix sim model generation for circuits with dangling nodes
9 months ago
Stefan Holst 9cebbcce8f support for storing responses separately
9 months ago
stefan 31434cfd51 4v sim, fixed 6v sim, better testing
9 months ago
stefan ce94210b52 adding more types
9 months ago
Stefan Holst 09420fd72c new logic sim interface prototype, simprim lib and test
10 months ago
Stefan Holst 5bcc1c1d77 new synthetic techlib with kyupy simprims
10 months ago
Stefan Holst df8a58f57b generate proper simprims in bench parser
10 months ago
Stefan Holst 3dfd0cb60d euivalence test, op format doc
10 months ago
Stefan Holst 21439e3595 circuit objects and nodes/lines of different circuits are not quivalent.
10 months ago
Stefan Holst 88a5c79161 dot fix and updated intro nb
10 months ago
Stefan Holst 9ca437fe47 fault injection for 4v sim, wave_sim test fix
10 months ago
Stefan Holst 0cdaf71963 fix for latest lark
10 months ago
Stefan Holst 75972d7bb2 numba config deprecated
10 months ago
Stefan Holst 469dc18aa9 lark dependency update
10 months ago