Tree: 469dc18aa9

devel

main

v0.0.1

v0.0.2

v0.0.3

v0.0.4

v0.0.5

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from '469dc18aa9'

${ noResults }

Commit Graph

2 Commits (469dc18aa9fd259fa9f264de5eabb15181e0a1b6)

Author	SHA1	Message	Date
Stefan Holst	351d809306	for release 0.0.4 ... - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements	2 years ago
stefan	63c0b48537	bump	3 years ago
Stefan Holst	08a22cf251	move sources to src, add package info and release 0.0.1	5 years ago