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60 MiB
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25 Commits (2bbdf3ee5db2472c34861a34ff25f9de38fd47f7)
 

Author SHA1 Message Date
Stefan Holst 2bbdf3ee5d fix logic sim of DFF.QN output
4 years ago
Stefan Holst 35cf63cf38 Make Node and Line indexable, documentation.
4 years ago
Stefan Holst ff4de6d782 de-lint and repr improvements
4 years ago
Stefan Holst c12a30328c better hr_time
4 years ago
Stefan Holst 7e6660002b support ibuff in WaveSim
4 years ago
Stefan Holst dfbc35eeb9 logging range fixes
4 years ago
Stefan Holst 4f531fe4cb implement logging range
4 years ago
Stefan Holst 18c17b5f76 more docs and reprs
4 years ago
Stefan Holst 0bad95e94e LogicSim clean-up and new fault injection facility. version bump.
4 years ago
Stefan Holst 7501613951 remove comments
4 years ago
Stefan Holst 5084f1dd8c demo nb run with cuda
4 years ago
Stefan Holst 7f035c1ac5 Migration to new logic value representation
4 years ago
Stefan Holst 7bcfbf502b Documentation, cleanup, multi-valued logic
4 years ago
Stefan Holst 5830608527 Documenting circuit module
4 years ago
Stefan Holst cff18e0915 start documentation
4 years ago
Stefan Holst a77ac4a397 start designing new data structures for m-valued logic
4 years ago
Stefan Holst 08a22cf251 move sources to src, add package info and release 0.0.1
4 years ago
Stefan Holst 765cb70ca3 add logic depth example
4 years ago
Stefan Holst e6ae009969 updated b14 benchmark, update wavesim capture api, expand usage examples
4 years ago
Stefan Holst e1101b5b70 fix loading of stuck-at fault patterns, support ibuff cell
4 years ago
Stefan Holst 6bba7ac359 support for stripping forks and memory re-use in wavesim.
4 years ago
Stefan Holst 1af346c97a overflow notification and wavecap statistics on GPU
4 years ago
Stefan Holst 3ad95153ab support more SAED cells, improve verilog parsing, fix inspection warnings
4 years ago
Stefan Holst 0c5a7f56e1 Project Import
4 years ago
s-holst 7a6ab750ca
Initial commit
4 years ago