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fix sim model gen for undriven outputs

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stefan committed 2026-05-11 23:46:18 +09:00
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src/kyupy/sim.py
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@@ -191,7 +191,7 @@ class SimOps:
root_nodes = set([n for n in circuit.s_nodes if len(n.ins) > 0] + [n for n in circuit.nodes if len(n.outs) == 0]) # start from POs, PPOs, and any dangling nodes root_nodes = set([n for n in circuit.s_nodes if len(n.ins) > 0] + [n for n in circuit.nodes if len(n.outs) == 0]) # start from POs, PPOs, and any dangling nodes
readers = np.array([1 if l.reader in root_nodes else len(l.reader.outs) for l in circuit.lines], dtype=np.int32) # for ref-counting forks readers = np.array([1 if l.reader in root_nodes else len(l.reader.outs) for l in circuit.lines], dtype=np.int32) # for ref-counting forks
level_lines = [n.ins[0] for n in root_nodes] level_lines = [n.ins[0] for n in root_nodes if len(n.ins) > 0 ]
# FIXME: Should probably instanciate buffers for PPOs and attach DFF clocks # FIXME: Should probably instanciate buffers for PPOs and attach DFF clocks
while len(level_lines) > 0: # traverse the circuit level-wise back towards (P)PIs while len(level_lines) > 0: # traverse the circuit level-wise back towards (P)PIs