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fix loading of stuck-at fault patterns, support ibuff cell

main
Stefan Holst 4 years ago
parent
commit
e1101b5b70
  1. 3
      kyupy/logic_sim.py
  2. 7
      kyupy/stil.py

3
kyupy/logic_sim.py

@ -23,6 +23,7 @@ class LogicSim:
self.input_vd1 = self.fork_vd1 self.input_vd1 = self.fork_vd1
self.output_vd1 = self.fork_vd1 self.output_vd1 = self.fork_vd1
self.inv_vd1 = self.not_vd1 self.inv_vd1 = self.not_vd1
self.ibuff_vd1 = self.not_vd1
self.nbuff_vd1 = self.fork_vd1 self.nbuff_vd1 = self.fork_vd1
self.xor2_vd1 = self.xor_vd1 self.xor2_vd1 = self.xor_vd1
@ -31,6 +32,7 @@ class LogicSim:
self.input_vd2 = self.fork_vd2 self.input_vd2 = self.fork_vd2
self.output_vd2 = self.fork_vd2 self.output_vd2 = self.fork_vd2
self.inv_vd2 = self.not_vd2 self.inv_vd2 = self.not_vd2
self.ibuff_vd2 = self.not_vd2
self.nbuff_vd2 = self.fork_vd2 self.nbuff_vd2 = self.fork_vd2
self.xor2_vd2 = self.xor_vd2 self.xor2_vd2 = self.xor_vd2
@ -39,6 +41,7 @@ class LogicSim:
self.input_vd3 = self.fork_vd3 self.input_vd3 = self.fork_vd3
self.output_vd3 = self.fork_vd3 self.output_vd3 = self.fork_vd3
self.inv_vd3 = self.not_vd3 self.inv_vd3 = self.not_vd3
self.ibuff_vd3 = self.not_vd3
self.nbuff_vd3 = self.fork_vd3 self.nbuff_vd3 = self.fork_vd3
self.xor2_vd3 = self.xor_vd3 self.xor2_vd3 = self.xor_vd3

7
kyupy/stil.py

@ -28,7 +28,7 @@ class StilFile:
for so_port in self.so_ports: for so_port in self.so_ports:
if so_port in call.parameters: if so_port in call.parameters:
unload[so_port] = call.parameters[so_port].replace('\n', '') unload[so_port] = call.parameters[so_port].replace('\n', '')
if len(capture) > 0: if len(launch) > 0:
self.patterns.append(ScanPattern(load, launch, capture, unload)) self.patterns.append(ScanPattern(load, launch, capture, unload))
capture = {} capture = {}
launch = {} launch = {}
@ -100,7 +100,7 @@ class StilFile:
if ('P' not in p.launch['_pi']) or ('P' not in p.capture['_pi']): if ('P' not in p.launch['_pi']) or ('P' not in p.capture['_pi']):
for si_port in self.si_ports.keys(): for si_port in self.si_ports.keys():
launch.set_values(i, p.load[si_port], scan_maps[si_port], scan_inversions[si_port]) launch.set_values(i, p.load[si_port], scan_maps[si_port], scan_inversions[si_port])
if 'P' in p.capture['_pi']: if '_pi' in p.capture and 'P' in p.capture['_pi']:
launch.set_values(i, p.capture['_pi'], pi_map) launch.set_values(i, p.capture['_pi'], pi_map)
return PackedVectors.from_pair(init, launch) return PackedVectors.from_pair(init, launch)
@ -109,7 +109,10 @@ class StilFile:
interface, pi_map, po_map, scan_maps, scan_inversions = self._maps(c) interface, pi_map, po_map, scan_maps, scan_inversions = self._maps(c)
resp = PackedVectors(len(self.patterns), len(interface), 2) resp = PackedVectors(len(self.patterns), len(interface), 2)
for i, p in enumerate(self.patterns): for i, p in enumerate(self.patterns):
if (len(p.capture) > 0):
resp.set_values(i, p.capture['_po'], po_map) resp.set_values(i, p.capture['_po'], po_map)
else:
resp.set_values(i, p.launch['_po'], po_map)
for so_port in self.so_ports.keys(): for so_port in self.so_ports.keys():
resp.set_values(i, p.unload[so_port], scan_maps[so_port], scan_inversions[so_port]) resp.set_values(i, p.unload[so_port], scan_maps[so_port], scan_inversions[so_port])
return resp return resp

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