fix stil loading and logic sim capture

Demo.ipynb

@@ -1009,7 +1009,7 @@
     {
      "data": {
       "text/plain": [
-       "119676"
+       "120628"
       ]
      },
      "execution_count": 36,
@@ -1195,7 +1195,7 @@
     {
      "data": {
       "text/plain": [
-       "2.0610005855560303"
+       "2.17240047454834"
       ]
      },
      "execution_count": 42,
@@ -1222,7 +1222,7 @@
     {
      "data": {
       "text/plain": [
-       "0.0"
+       "2.0"
       ]
      },
      "execution_count": 43,
@@ -1286,13 +1286,17 @@
      "name": "stdout",
      "output_type": "stream",
      "text": [
-      "Found 1 CUDA devices\n",
-      "id 0              b'TITAN V'                              [SUPPORTED]\n",
+      "Found 2 CUDA devices\n",
+      "id 0    b'NVIDIA GeForce RTX 3090'                              [SUPPORTED]\n",
+      "                      compute capability: 8.6\n",
+      "                           pci device id: 0\n",
+      "                              pci bus id: 3\n",
+      "id 1       b'NVIDIA TITAN V'                              [SUPPORTED]\n",
       "                      compute capability: 7.0\n",
       "                           pci device id: 0\n",
       "                              pci bus id: 2\n",
       "Summary:\n",
-      "\t1/1 devices are supported\n"
+      "\t2/2 devices are supported\n"
      ]
     },
     {
@@ -1322,9 +1326,9 @@
  ],
  "metadata": {
   "kernelspec": {
-   "display_name": "Python 3",
+   "display_name": "worker",
    "language": "python",
-   "name": "python3"
+   "name": "worker"
   },
   "language_info": {
    "codemirror_mode": {
@@ -1336,7 +1340,7 @@
    "name": "python",
    "nbconvert_exporter": "python",
    "pygments_lexer": "ipython3",
-   "version": "3.6.8"
+   "version": "3.6.13"
   }
  },
  "nbformat": 4,

src/kyupy/logic_sim.py

@@ -106,14 +106,15 @@ class LogicSim:
                 resp[...] = self.state[node.outs[0]]
             else:
                 resp[...] = self.state[node.ins[0]]
-            if self.m > 2 and 'dff' in node.kind.lower() and len(node.outs) > 0:
-                if node.outs[0] is None:
-                    resp[1, :] = ~self.state[node.outs[1], 0, :]  # assume QN is connected, take inverse of that.
-                else:
-                    resp[1, :] = self.state[node.outs[0], 0, :]
-                if self.m > 4:
-                    resp[..., 2, :] = resp[..., 0, :] ^ resp[..., 1, :]
-                # We don't handle X or - correctly.
+            # FIXME: unclear why we should use outs for DFFs
+            #if self.m > 2 and 'dff' in node.kind.lower() and len(node.outs) > 0:
+            #    if node.outs[0] is None:
+            #        resp[1, :] = ~self.state[node.outs[1], 0, :]  # assume QN is connected, take inverse of that.
+            #    else:
+            #        resp[1, :] = self.state[node.outs[0], 0, :]
+            #    if self.m > 4:
+            #        resp[..., 2, :] = resp[..., 0, :] ^ resp[..., 1, :]
+            #    # We don't handle X or - correctly.
 
         return responses
 

src/kyupy/stil.py

@@ -114,7 +114,7 @@ class StilFile:
             for si_port in self.si_ports.keys():
                 pattern = logic.mv_xor(p.load[si_port], scan_inversions[si_port])
                 init.data[scan_maps[si_port], i] = pattern.data[:, 0]
-            init.data[pi_map, i] = logic.MVArray(p.launch['_pi']).data[:, 0]
+            init.data[pi_map, i] = logic.MVArray(p.launch['_pi'] if '_pi' in p.launch else p.capture['_pi']).data[:, 0]
         launch_bp = logic.BPArray(init)
         sim4v = LogicSim(circuit, len(init), m=4)
         sim4v.assign(launch_bp)
@@ -122,8 +122,8 @@ class StilFile:
         sim4v.capture(launch_bp)
         launch = logic.MVArray(launch_bp)
         for i, p in enumerate(self.patterns):
-            # if there was no launch clock, then init = launch
-            if ('P' not in p.launch['_pi']) or ('P' not in p.capture['_pi']):
+            # if there was no launch cycle or launch clock, then init = launch
+            if '_pi' not in p.launch or 'P' not in p.launch['_pi'] or 'P' not in p.capture['_pi']:
                 for si_port in self.si_ports.keys():
                     pattern = logic.mv_xor(p.load[si_port], scan_inversions[si_port])
                     launch.data[scan_maps[si_port], i] = pattern.data[:, 0]

tests/test_logic_sim.py

@@ -75,9 +75,9 @@ def test_8v():
 
 def test_loop():
     c = bench.parse('q=dff(d) d=not(q)')
-    s = LogicSim(c, 2, m=8)
+    s = LogicSim(c, 4, m=8)
     assert len(s.interface) == 1
-    mva = MVArray([['0'], ['1']], m=8)
+    mva = MVArray([['0'], ['1'], ['R'], ['F']], m=8)
 
     s.assign(BPArray(mva))
     s.propagate()
@@ -85,14 +85,18 @@ def test_loop():
     s.capture(resp_bp)
     resp = MVArray(resp_bp)
 
-    assert resp[0] == 'R'
-    assert resp[1] == 'F'
+    assert resp[0] == '1'
+    assert resp[1] == '0'
+    assert resp[2] == 'F'
+    assert resp[3] == 'R'
 
     resp_bp = s.cycle(resp_bp)
     resp = MVArray(resp_bp)
 
-    assert resp[0] == 'F'
-    assert resp[1] == 'R'
+    assert resp[0] == '0'
+    assert resp[1] == '1'
+    assert resp[2] == 'R'
+    assert resp[3] == 'F'
 
 
 def test_latch():

tests/test_stil.py

@@ -13,9 +13,9 @@ def test_b14(mydir):
     assert len(tests) > 0
     assert len(resp) > 0
     
-    #s2 = stil.load(mydir / 'b14.transition.stil.gz')
-    #tests = s2.tests_loc(b14)
-    #resp = s2.responses(b14)
-    #assert len(tests) > 0
-    #assert len(resp) > 0
+    s2 = stil.load(mydir / 'b14.transition.stil.gz')
+    tests = s2.tests_loc(b14)
+    resp = s2.responses(b14)
+    assert len(tests) > 0
+    assert len(resp) > 0