for release 0.0.6

- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API)
- sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic
- Circuit: dot output fix and better style, fixed equivalence check of lines and nodes.
- Techlib: Added KYUPY library with supported simulation primitives for debug and testing
- tests: fixed and added more for better coverage
- more type annotations
- updated project config and dependencies for better uv experience, newer lark, newer numpy

.gitignore

@@ -1,12 +1,14 @@
-__pycache__
+__pycache__/
 .ipynb_checkpoints
 .pytest_cache
 .DS_Store
-*.pyc
-docs/_build
-build
-dist
 .idea
 .vscode
-src/kyupy.egg-info
+.venv
+*.py[oc]
+docs/_build
+build/
+dist/
+wheels/
+*.egg-info
 *nogit*