stefan
d247115744
- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API) - sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic - Circuit: dot output fix and better style, fixed equivalence check of lines and nodes. - Techlib: Added KYUPY library with supported simulation primitives for debug and testing - tests: fixed and added more for better coverage - more type annotations - updated project config and dependencies for better uv experience, newer lark, newer numpy
15 lines
137 B
Plaintext
15 lines
137 B
Plaintext
__pycache__/
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.ipynb_checkpoints
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.pytest_cache
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.DS_Store
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.idea
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.vscode
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.venv
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*.py[oc]
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docs/_build
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build/
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dist/
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wheels/
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*.egg-info
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*nogit*
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