capitalize tech libs
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@@ -134,7 +134,7 @@ class TechLibNew:
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circuit.substitute(n, self.cells[n.kind][0])
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circuit.substitute(n, self.cells[n.kind][0])
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nangate = TechLibNew(r"""
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NANGATE = TechLibNew(r"""
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FILLCELL_X{1,2,4,8,16,32} ;
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FILLCELL_X{1,2,4,8,16,32} ;
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LOGIC0_X1 output(Z) Z=__const0__() ;
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LOGIC0_X1 output(Z) Z=__const0__() ;
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@@ -207,7 +207,7 @@ DLL_X{1,2} input(D,GN) output(Q) G=INV1(GN) Q=LATCH(D,G) ;
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# SAED90nm and SAED32nm libraries.
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# SAED90nm and SAED32nm libraries.
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# not included here: negative-edge flip-flops, tri-state, latches, clock gating, level shifters
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# not included here: negative-edge flip-flops, tri-state, latches, clock gating, level shifters
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saed90 = TechLibNew(r"""
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SAED90 = TechLibNew(r"""
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NBUFFX{2,4,8,16,32}$ input(INP) output(Z) Z=BUF1(INP) ;
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NBUFFX{2,4,8,16,32}$ input(INP) output(Z) Z=BUF1(INP) ;
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AOBUFX{1,2,4}$ input(INP) output(Z) Z=BUF1(INP) ;
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AOBUFX{1,2,4}$ input(INP) output(Z) Z=BUF1(INP) ;
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DELLN{1,2,3}X2$ input(INP) output(Z)Z=BUF1(INP) ;
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DELLN{1,2,3}X2$ input(INP) output(Z)Z=BUF1(INP) ;
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@@ -294,7 +294,7 @@ LATCHX{1,2}$ input(D,CLK) output(Q,QN) Q=LATCH(D,CLK) QN=INV1(Q) ;
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""".replace('$','{,_LVT,_HVT}'))
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""".replace('$','{,_LVT,_HVT}'))
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saed32 = TechLibNew(r"""
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SAED32 = TechLibNew(r"""
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NBUFFX{2,4,8,16,32}$ input(A) output(Y) Y=BUF1(A) ;
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NBUFFX{2,4,8,16,32}$ input(A) output(Y) Y=BUF1(A) ;
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AOBUFX{1,2,4}$ input(A) output(Y) Y=BUF1(A) ;
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AOBUFX{1,2,4}$ input(A) output(Y) Y=BUF1(A) ;
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DELLN{1,2,3}X2$ input(A) output(Y) Y=BUF1(A) ;
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DELLN{1,2,3}X2$ input(A) output(Y) Y=BUF1(A) ;
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