Circuit pickle, STIL/SDF/techlib fixes, sdata
- fix pin indices for various SC lib variants - SDF annotation improvements - STIL loading improvements - Support for per-simulation parameters in WaveSim - Circuit is now pickleable and comparable
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Stefan Holst committed
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840b816804
16 files changed
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-110
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+12
-1
@@ -1,5 +1,7 @@
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from kyupy.circuit import Circuit, Node, Line
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import pickle
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from kyupy.circuit import Circuit, Node, Line
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from kyupy import verilog
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def test_lines():
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c = Circuit()
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@@ -99,3 +101,12 @@ def test_circuit():
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for n in c.topological_order():
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repr(n)
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def test_pickle(mydir):
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c = verilog.load(mydir / 'b14.v.gz')
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assert c is not None
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cs = pickle.dumps(c)
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assert cs is not None
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c2 = pickle.loads(cs)
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assert c == c2
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@@ -145,6 +145,20 @@ def test_mv_operations():
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assert lg.mv_xor(x1_4v, x2_4v)[0] == '0XX1XXXXXXXX1XX0'
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assert lg.mv_xor(x1_8v, x2_8v)[0] == '0XX1PRFNXXXXXXXXXXXXXXXX1XX0NFRPPXXNPRFNRXXFRPNFFXXRFNPRNXXPNFRP'
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x30_2v = lg.MVArray("0000", m=2)
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x31_2v = lg.MVArray("1111", m=2)
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x30_4v = lg.MVArray("0000000000000000", m=4)
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x31_4v = lg.MVArray("1111111111111111", m=4)
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x30_8v = lg.MVArray("0000000000000000000000000000000000000000000000000000000000000000", m=8)
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x31_8v = lg.MVArray("1111111111111111111111111111111111111111111111111111111111111111", m=8)
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assert lg.mv_latch(x1_2v, x2_2v, x30_2v)[0] == '0001'
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assert lg.mv_latch(x1_2v, x2_2v, x31_2v)[0] == '1011'
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assert lg.mv_latch(x1_4v, x2_4v, x30_4v)[0] == '0XX00XXX0XXX0XX1'
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assert lg.mv_latch(x1_4v, x2_4v, x31_4v)[0] == '1XX01XXX1XXX1XX1'
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assert lg.mv_latch(x1_8v, x2_8v, x30_8v)[0] == '0XX000000XXXXXXX0XXXXXXX0XX10R110XX000000XXR0R0R0XXF001F0XX10R11'
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assert lg.mv_latch(x1_8v, x2_8v, x31_8v)[0] == '1XX01F001XXXXXXX1XXXXXXX1XX111111XX01F001XXR110R1XXF1F1F1XX11111'
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def test_bparray():
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@@ -212,3 +226,27 @@ def test_bparray():
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assert lg.MVArray(out_2v)[0] == '0110'
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assert lg.MVArray(out_4v)[0] == '0XX1XXXXXXXX1XX0'
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assert lg.MVArray(out_8v)[0] == '0XX1PRFNXXXXXXXXXXXXXXXX1XX0NFRPPXXNPRFNRXXFRPNFFXXRFNPRNXXPNFRP'
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x30_2v = lg.BPArray("0000", m=2)
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x30_4v = lg.BPArray("0000000000000000", m=4)
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x30_8v = lg.BPArray("0000000000000000000000000000000000000000000000000000000000000000", m=8)
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lg.bp_latch(out_2v.data, x1_2v.data, x2_2v.data, x30_2v.data)
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lg.bp_latch(out_4v.data, x1_4v.data, x2_4v.data, x30_4v.data)
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lg.bp_latch(out_8v.data, x1_8v.data, x2_8v.data, x30_8v.data)
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assert lg.MVArray(out_2v)[0] == '0001'
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assert lg.MVArray(out_4v)[0] == '0XX00XXX0XXX0XX1'
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assert lg.MVArray(out_8v)[0] == '0XX000000XXXXXXX0XXXXXXX0XX10R110XX000000XXR0R0R0XXF001F0XX10R11'
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x31_2v = lg.BPArray("1111", m=2)
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x31_4v = lg.BPArray("1111111111111111", m=4)
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x31_8v = lg.BPArray("1111111111111111111111111111111111111111111111111111111111111111", m=8)
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lg.bp_latch(out_2v.data, x1_2v.data, x2_2v.data, x31_2v.data)
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lg.bp_latch(out_4v.data, x1_4v.data, x2_4v.data, x31_4v.data)
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lg.bp_latch(out_8v.data, x1_8v.data, x2_8v.data, x31_8v.data)
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assert lg.MVArray(out_2v)[0] == '1011'
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assert lg.MVArray(out_4v)[0] == '1XX01XXX1XXX1XX1'
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assert lg.MVArray(out_8v)[0] == '1XX01F001XXXXXXX1XXXXXXX1XX111111XX01F001XXR110R1XXF1F1F1XX11111'
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@@ -73,6 +73,45 @@ def test_8v():
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assert resp[i] == mva[i]
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def test_loop():
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c = bench.parse('q=dff(d) d=not(q)')
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s = LogicSim(c, 4, m=8)
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assert len(s.interface) == 1
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mva = MVArray([['0'], ['1'], ['R'], ['F']], m=8)
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s.assign(BPArray(mva))
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s.propagate()
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resp_bp = BPArray((len(s.interface), s.sims))
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s.capture(resp_bp)
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resp = MVArray(resp_bp)
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assert resp[0] == '1'
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assert resp[1] == '0'
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assert resp[2] == 'F'
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assert resp[3] == 'R'
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resp_bp = s.cycle(resp_bp)
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resp = MVArray(resp_bp)
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assert resp[0] == '0'
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assert resp[1] == '1'
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assert resp[2] == 'R'
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assert resp[3] == 'F'
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def test_latch():
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c = bench.parse('input(d, t) output(q) q=latch(d, t)')
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s = LogicSim(c, 8, m=8)
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assert len(s.interface) == 4
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mva = MVArray(['00-0', '00-1', '01-0', '01-1', '10-0', '10-1', '11-0', '11-1'], m=8)
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exp = MVArray(['0000', '0011', '0100', '0100', '1000', '1011', '1111', '1111'], m=8)
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resp = MVArray(s.cycle(BPArray(mva)))
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for i in range(len(mva)):
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assert resp[i] == exp[i]
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def test_b01(mydir):
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c = bench.load(mydir / 'b01.bench')
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+14
-1
@@ -1,8 +1,21 @@
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from kyupy import stil
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from kyupy import stil, verilog
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def test_b14(mydir):
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b14 = verilog.load(mydir / 'b14.v.gz')
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s = stil.load(mydir / 'b14.stuck.stil.gz')
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assert len(s.signal_groups) == 10
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assert len(s.scan_chains) == 1
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assert len(s.calls) == 2163
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tests = s.tests(b14)
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resp = s.responses(b14)
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assert len(tests) > 0
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assert len(resp) > 0
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s2 = stil.load(mydir / 'b14.transition.stil.gz')
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tests = s2.tests_loc(b14)
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resp = s2.responses(b14)
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assert len(tests) > 0
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assert len(resp) > 0
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+11
-9
@@ -29,20 +29,22 @@ def test_wave_eval():
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sat[1] = 16, 16, 0
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sat[2] = 32, 16, 0
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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sdata = np.asarray([1, -1, 0, 0], dtype='float32')
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == TMIN
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a[0] = TMIN
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == TMIN
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b[0] = TMIN
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == TMAX
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a[0] = 1 # A _/^^^
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b[0] = 2 # B __/^^
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == TMIN # ^^^\___ B -> Z fall delay
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assert z[1] == 2.4
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assert z[2] == TMAX
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@@ -50,7 +52,7 @@ def test_wave_eval():
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a[0] = TMIN # A ^^^^^^
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b[0] = TMIN # B ^^^\__
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b[1] = 2
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == 2.3 # ___/^^^ B -> Z rise delay
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assert z[1] == TMAX
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@@ -59,7 +61,7 @@ def test_wave_eval():
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b[0] = TMIN
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b[1] = 2 # B ^^\__/^^
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b[2] = 2.35
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == 2.3 # __/^^\__
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assert z[1] == 2.75
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assert z[2] == TMAX
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@@ -69,7 +71,7 @@ def test_wave_eval():
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b[0] = 2 # B __/^^\__
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b[1] = 2.45
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b[2] = TMAX
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == TMIN # ^^\__/^^
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assert z[1] == 2.4
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assert z[2] == 2.75
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@@ -80,7 +82,7 @@ def test_wave_eval():
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b[0] = 2 # B __/^^\__
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b[1] = 2.35
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b[2] = TMAX
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == TMIN # ^^^^^^
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assert z[1] == TMAX
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@@ -89,7 +91,7 @@ def test_wave_eval():
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b[0] = TMIN
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b[1] = 2 # B ^^\__/^^
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b[2] = 2.25
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times)
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wave_eval((0b0111, 2, 0, 1), state, sat, 0, line_times, sdata)
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assert z[0] == TMAX # ______
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