improve robustness of sdf annotation and wave sim
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8bbaaf8fae
commit
7c03271048
2 files changed
+17
-10
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+15
-9
@@ -92,7 +92,7 @@ class DelayFile:
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continue
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continue
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cell = find_cell(cn)
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cell = find_cell(cn)
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if cell is None:
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if cell is None:
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log.warn(f'Cell from SDF not found in circuit: {cn}')
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#log.warn(f'Cell from SDF not found in circuit: {cn}')
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continue
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continue
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ipn = re.sub(r'\((neg|pos)edge ([^)]+)\)', r'\2', ipn)
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ipn = re.sub(r'\((neg|pos)edge ([^)]+)\)', r'\2', ipn)
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ipin = tlib.pin_index(cell.kind, ipn)
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ipin = tlib.pin_index(cell.kind, ipn)
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@@ -111,12 +111,15 @@ class DelayFile:
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if ffdelays and (len(cell.outs) > opin):
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if ffdelays and (len(cell.outs) > opin):
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add_delays(cell.outs[opin])
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add_delays(cell.outs[opin])
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else:
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else:
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if kind.startswith(('xor', 'xnor')):
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if ipin < len(cell.ins):
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# print(ipn, ipin, times[cell.i_lines[ipin], 0, 0])
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if kind.startswith(('xor', 'xnor')):
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take_avg = timing[cell.ins[ipin]].sum() > 0
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# print(ipn, ipin, times[cell.i_lines[ipin], 0, 0])
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add_delays(cell.ins[ipin])
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take_avg = timing[cell.ins[ipin]].sum() > 0
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if take_avg:
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add_delays(cell.ins[ipin])
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timing[cell.ins[ipin]] /= 2
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if take_avg:
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timing[cell.ins[ipin]] /= 2
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else:
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log.warn(f'No line to annotate pin {ipn} of {cell}')
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if not interconnect or self.interconnects is None:
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if not interconnect or self.interconnects is None:
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return timing
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return timing
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@@ -139,14 +142,17 @@ class DelayFile:
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cn2, pn2 = (n2, 'IN')
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cn2, pn2 = (n2, 'IN')
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c1 = find_cell(cn1)
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c1 = find_cell(cn1)
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if c1 is None:
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if c1 is None:
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log.warn(f'Cell from SDF not found in circuit: {cn1}')
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#log.warn(f'Cell from SDF not found in circuit: {cn1}')
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continue
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continue
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c2 = find_cell(cn2)
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c2 = find_cell(cn2)
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if c2 is None:
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if c2 is None:
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log.warn(f'Cell from SDF not found in circuit: {cn2}')
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#log.warn(f'Cell from SDF not found in circuit: {cn2}')
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continue
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continue
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p1, p2 = tlib.pin_index(c1.kind, pn1), tlib.pin_index(c2.kind, pn2)
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p1, p2 = tlib.pin_index(c1.kind, pn1), tlib.pin_index(c2.kind, pn2)
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line = None
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line = None
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if len(c2.ins) <= p2:
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log.warn(f'No line to annotate pin {pn2} of {c2}')
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continue
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f1, f2 = c1.outs[p1].reader, c2.ins[p2].driver
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f1, f2 = c1.outs[p1].reader, c2.ins[p2].driver
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if f1 != f2: # possible branchfork
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if f1 != f2: # possible branchfork
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assert len(f2.ins) == 1
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assert len(f2.ins) == 1
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@@ -161,7 +161,8 @@ class WaveSim:
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if kind == '__fork__':
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if kind == '__fork__':
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if not strip_forks:
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if not strip_forks:
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for o_line in n.outs:
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for o_line in n.outs:
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ops.append((0b1010, o_line.index, i0_idx, i1_idx))
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if o_line is not None:
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ops.append((0b1010, o_line.index, i0_idx, i1_idx))
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elif kind.startswith('nand'):
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elif kind.startswith('nand'):
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ops.append((0b0111, o0_idx, i0_idx, i1_idx))
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ops.append((0b0111, o0_idx, i0_idx, i1_idx))
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elif kind.startswith('nor'):
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elif kind.startswith('nor'):
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