From 7c032710480e620d1bc960158bbda88af41d6dba Mon Sep 17 00:00:00 2001
From: Stefan Holst <holst@ci.kyutech.ac.jp>
Date: Wed, 1 Sep 2021 12:57:55 +0900
Subject: [PATCH] improve robustness of sdf annotation and wave sim

---
 src/kyupy/sdf.py      | 24 +++++++++++++++---------
 src/kyupy/wave_sim.py |  3 ++-
 2 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/src/kyupy/sdf.py b/src/kyupy/sdf.py
index 78715f7..c1e3ebf 100644
--- a/src/kyupy/sdf.py
+++ b/src/kyupy/sdf.py
@@ -92,7 +92,7 @@ class DelayFile:
                     continue
                 cell = find_cell(cn)
                 if cell is None:
-                    log.warn(f'Cell from SDF not found in circuit: {cn}')
+                    #log.warn(f'Cell from SDF not found in circuit: {cn}')
                     continue
                 ipn = re.sub(r'\((neg|pos)edge ([^)]+)\)', r'\2', ipn)
                 ipin = tlib.pin_index(cell.kind, ipn)
@@ -111,12 +111,15 @@ class DelayFile:
                     if ffdelays and (len(cell.outs) > opin):
                         add_delays(cell.outs[opin])
                 else:
-                    if kind.startswith(('xor', 'xnor')):
-                        # print(ipn, ipin, times[cell.i_lines[ipin], 0, 0])
-                        take_avg = timing[cell.ins[ipin]].sum() > 0
-                    add_delays(cell.ins[ipin])
-                    if take_avg:
-                        timing[cell.ins[ipin]] /= 2
+                    if ipin < len(cell.ins):
+                        if kind.startswith(('xor', 'xnor')):
+                            # print(ipn, ipin, times[cell.i_lines[ipin], 0, 0])
+                            take_avg = timing[cell.ins[ipin]].sum() > 0
+                        add_delays(cell.ins[ipin])
+                        if take_avg:
+                            timing[cell.ins[ipin]] /= 2
+                    else:
+                        log.warn(f'No line to annotate pin {ipn} of {cell}')
 
         if not interconnect or self.interconnects is None:
             return timing
@@ -139,14 +142,17 @@ class DelayFile:
                 cn2, pn2 = (n2, 'IN')
             c1 = find_cell(cn1)
             if c1 is None:
-                log.warn(f'Cell from SDF not found in circuit: {cn1}')
+                #log.warn(f'Cell from SDF not found in circuit: {cn1}')
                 continue
             c2 = find_cell(cn2)
             if c2 is None:
-                log.warn(f'Cell from SDF not found in circuit: {cn2}')
+                #log.warn(f'Cell from SDF not found in circuit: {cn2}')
                 continue
             p1, p2 = tlib.pin_index(c1.kind, pn1), tlib.pin_index(c2.kind, pn2)
             line = None
+            if len(c2.ins) <= p2:
+                log.warn(f'No line to annotate pin {pn2} of {c2}')
+                continue
             f1, f2 = c1.outs[p1].reader, c2.ins[p2].driver
             if f1 != f2:  # possible branchfork
                 assert len(f2.ins) == 1
diff --git a/src/kyupy/wave_sim.py b/src/kyupy/wave_sim.py
index 3412d5c..8ce37c3 100644
--- a/src/kyupy/wave_sim.py
+++ b/src/kyupy/wave_sim.py
@@ -161,7 +161,8 @@ class WaveSim:
                 if kind == '__fork__':
                     if not strip_forks:
                         for o_line in n.outs:
-                            ops.append((0b1010, o_line.index, i0_idx, i1_idx))
+                            if o_line is not None:
+                                ops.append((0b1010, o_line.index, i0_idx, i1_idx))
                 elif kind.startswith('nand'):
                     ops.append((0b0111, o0_idx, i0_idx, i1_idx))
                 elif kind.startswith('nor'):