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new synthetic techlib with kyupy simprims

devel
Stefan Holst 2 days ago
parent
df8a58f57b
commit
5bcc1c1d77
2 changed files with 44 additions and 7 deletions
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  1. 40
      src/kyupy/techlib.py
  2. 11
      src/kyupy/verilog.py

40
src/kyupy/techlib.py
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@ -64,6 +64,44 @@ class TechLib:
return self.cells[kind][1][pin][1] return self.cells[kind][1][pin][1]
KYUPY = TechLib(r"""
BUF1 input(i0) output(o) o=BUF1(i0) ;
INV1 input(i0) output(o) o=INV1(i0) ;
AND2 input(i0,i1) output(o) o=AND2(i0,i1) ;
AND3 input(i0,i1,i2) output(o) o=AND3(i0,i1,i2) ;
AND4 input(i0,i1,i2,i3) output(o) o=AND4(i0,i1,i2,i3) ;
NAND2 input(i0,i1) output(o) o=NAND2(i0,i1) ;
NAND3 input(i0,i1,i2) output(o) o=NAND3(i0,i1,i2) ;
NAND4 input(i0,i1,i2,i3) output(o) o=NAND4(i0,i1,i2,i3);
OR2 input(i0,i1) output(o) o=OR2(i0,i1) ;
OR3 input(i0,i1,i2) output(o) o=OR3(i0,i1,i2) ;
OR4 input(i0,i1,i2,i3) output(o) o=OR4(i0,i1,i2,i3) ;
NOR2 input(i0,i1) output(o) o=NOR2(i0,i1) ;
NOR3 input(i0,i1,i2) output(o) o=NOR3(i0,i1,i2) ;
NOR4 input(i0,i1,i2,i3) output(o) o=NOR4(i0,i1,i2,i3) ;
XOR2 input(i0,i1) output(o) o=XOR2(i0,i1) ;
XOR3 input(i0,i1,i2) output(o) o=XOR3(i0,i1,i2) ;
XOR4 input(i0,i1,i2,i3) output(o) o=XOR4(i0,i1,i2,i3) ;
XNOR2 input(i0,i1) output(o) o=XNOR2(i0,i1) ;
XNOR3 input(i0,i1,i2) output(o) o=XNOR3(i0,i1,i2) ;
XNOR4 input(i0,i1,i2,i3) output(o) o=XNOR4(i0,i1,i2,i3) ;
AO21 input(i0,i1,i2) output(o) o=AO21(i0,i1,i2) ;
AO22 input(i0,i1,i2,i3) output(o) o=AO22(i0,i1,i2,i3) ;
OA21 input(i0,i1,i2) output(o) o=OA21(i0,i1,i2) ;
OA22 input(i0,i1,i2,i3) output(o) o=OA22(i0,i1,i2,i3) ;
AOI21 input(i0,i1,i2) output(o) o=AOI21(i0,i1,i2) ;
AOI22 input(i0,i1,i2,i3) output(o) o=AOI22(i0,i1,i2,i3) ;
OAI21 input(i0,i1,i2) output(o) o=OAI21(i0,i1,i2) ;
OAI22 input(i0,i1,i2,i3) output(o) o=OAI22(i0,i1,i2,i3) ;
AO211 input(i0,i1,i2,i3) output(o) o=AO211(i0,i1,i2,i3) ;
OA211 input(i0,i1,i2,i3) output(o) o=OA211(i0,i1,i2,i3) ;
AOI211 input(i0,i1,i2,i3) output(o) o=AOI211(i0,i1,i2,i3) ;
OAI211 input(i0,i1,i2,i3) output(o) o=OAI211(i0,i1,i2,i3) ;
MUX21 input(i0,i1,i2) output(o) o=MUX21(i0,i1,i2) ;
""")
"""A synthetic library of all KyuPy simulation primitives.
"""
GSC180 = TechLib(r""" GSC180 = TechLib(r"""
BUFX{1,3} input(A) output(Y) Y=BUF1(A) ; BUFX{1,3} input(A) output(Y) Y=BUF1(A) ;
CLKBUFX{1,2,3} input(A) output(Y) Y=BUF1(A) ; CLKBUFX{1,2,3} input(A) output(Y) Y=BUF1(A) ;
@ -326,7 +364,7 @@ It defines all cells except: negative-edge flip-flops, tri-state, latches, clock
SAED90 = TechLib(r""" SAED90 = TechLib(r"""
NBUFFX{2,4,8,16,32}$ input(INP) output(Z) Z=BUF1(INP) ; NBUFFX{2,4,8,16,32}$ input(INP) output(Z) Z=BUF1(INP) ;
AOBUFX{1,2,4}$ input(INP) output(Z) Z=BUF1(INP) ; AOBUFX{1,2,4}$ input(INP) output(Z) Z=BUF1(INP) ;
DELLN{1,2,3}X2$ input(INP) output(Z)Z=BUF1(INP) ; DELLN{1,2,3}X2$ input(INP) output(Z) Z=BUF1(INP) ;
INVX{0,1,2,4,8,16,32}$ input(INP) output(ZN) ZN=INV1(INP) ; INVX{0,1,2,4,8,16,32}$ input(INP) output(ZN) ZN=INV1(INP) ;
AOINVX{1,2,4}$ input(INP) output(ZN) ZN=INV1(INP) ; AOINVX{1,2,4}$ input(INP) output(ZN) ZN=INV1(INP) ;

11
src/kyupy/verilog.py
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@ -10,7 +10,7 @@ from lark import Lark, Transformer, Tree
from . import log, readtext from . import log, readtext
from .circuit import Circuit, Node, Line from .circuit import Circuit, Node, Line
from .techlib import NANGATE from .techlib import KYUPY
Instantiation = namedtuple('Instantiation', ['type', 'name', 'pins']) Instantiation = namedtuple('Instantiation', ['type', 'name', 'pins'])
@ -35,7 +35,7 @@ class SignalDeclaration:
class VerilogTransformer(Transformer): class VerilogTransformer(Transformer):
def __init__(self, branchforks=False, tlib=NANGATE): def __init__(self, branchforks=False, tlib=KYUPY):
super().__init__() super().__init__()
self.branchforks = branchforks self.branchforks = branchforks
self.tlib = tlib self.tlib = tlib
@ -96,8 +96,7 @@ class VerilogTransformer(Transformer):
sel = args[0] sel = args[0]
ctrue = args[1] ctrue = args[1]
cfalse = args[2] cfalse = args[2]
print(f"got ternary if {args[0]} {args[1]}") log.warn(f"FIXME: not implemented: ternary if {args[0]} {args[1]}")
return args[1] return args[1]
def declaration(self, kind, args): def declaration(self, kind, args):
@ -259,7 +258,7 @@ GRAMMAR = r"""
""" """
def parse(text, tlib=NANGATE, branchforks=False): def parse(text, tlib=KYUPY, branchforks=False):
"""Parses the given ``text`` as Verilog code. """Parses the given ``text`` as Verilog code.
:param text: A string with Verilog code. :param text: A string with Verilog code.
@ -273,7 +272,7 @@ def parse(text, tlib=NANGATE, branchforks=False):
return Lark(GRAMMAR, parser="lalr", transformer=VerilogTransformer(branchforks, tlib)).parse(text) return Lark(GRAMMAR, parser="lalr", transformer=VerilogTransformer(branchforks, tlib)).parse(text)
def load(file, tlib=NANGATE, branchforks=False): def load(file, tlib=KYUPY, branchforks=False):
"""Parses the contents of ``file`` as Verilog code. """Parses the contents of ``file`` as Verilog code.
:param file: A file name or a file handle. Files with `.gz`-suffix are decompressed on-the-fly. :param file: A file name or a file handle. Files with `.gz`-suffix are decompressed on-the-fly.

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