support more SAED cells, improve verilog parsing, fix inspection warnings
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Stefan Holst committed
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0c5a7f56e1
commit
3ad95153ab
4 files changed
+130
-12
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@@ -45,6 +45,7 @@ class MockCuda:
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self.y = 0
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def jit(self, device=False):
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_ = device # silence "not used" warning
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outer = self
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def make_launcher(func):
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@@ -84,6 +85,7 @@ class MockCuda:
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pass
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def grid(self, dims):
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_ = dims # silence "not used" warning
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return self.x, self.y
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+111
-7
@@ -2,10 +2,14 @@ from kyupy.circuit import Node, Line
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def pin_index(cell_type, pin):
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if cell_type.startswith('HADD') and pin == 'B0': return 1
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if cell_type.startswith('HADD') and pin == 'SO': return 1
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if cell_type.startswith('MUX21') and pin == 'S': return 2
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if cell_type.startswith('SDFF') and pin == 'QN': return 1
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if cell_type.startswith('DFF') and pin == 'QN': return 1
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if cell_type.startswith('DFF') and pin == 'CLK': return 1
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if cell_type.startswith('DFF') and pin == 'RSTB': return 2
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if cell_type.startswith('DFF') and pin == 'SETB': return 3
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if pin in ['A2', 'IN2', 'SE', 'B', 'CO']: return 1
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if pin in ['A3', 'IN3', 'SI', 'CI']: return 2
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if pin == 'A4' or pin == 'IN4' or pin == 'CLK': return 3 # CLK for scan cells SDFF
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@@ -17,7 +21,7 @@ def pin_index(cell_type, pin):
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def pin_is_output(kind, pin):
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if 'MUX' in kind and pin == 'S':
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return False
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return pin in ['Q', 'QN', 'Z', 'ZN', 'Y', 'CO', 'S']
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return pin in ['Q', 'QN', 'Z', 'ZN', 'Y', 'CO', 'S', 'SO', 'C1']
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def add_and_connect(circuit, name, kind, in1=None, in2=None, out=None):
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@@ -58,7 +62,7 @@ def split_complex_gates(circuit):
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n_or = add_and_connect(circuit, name+'~or', 'OR2', ins[0], ins[1], None)
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n_and = add_and_connect(circuit, name+'~and', 'AND2', None, ins[2], outs[0])
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Line(circuit, n_or, n_and)
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elif n.kind.startswith('OAI21'):
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elif n.kind.startswith('OAI21X'):
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n.remove()
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n_or = add_and_connect(circuit, name+'~or', 'OR2', ins[0], ins[1], None)
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n_nand = add_and_connect(circuit, name+'~nand', 'NAND2', None, ins[2], outs[0])
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@@ -70,6 +74,13 @@ def split_complex_gates(circuit):
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n_and = add_and_connect(circuit, name+'~and', 'AND2', None, None, outs[0])
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Line(circuit, n_or0, n_and)
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Line(circuit, n_or1, n_and)
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elif n.kind.startswith('OAI22X'):
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n.remove()
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n_nand = add_and_connect(circuit, name+'~nand', 'NAND2', None, None, outs[0])
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Line(circuit, n_or0, n_nand)
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Line(circuit, n_or1, n_nand)
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elif n.kind.startswith('AO22X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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@@ -77,6 +88,13 @@ def split_complex_gates(circuit):
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n_or = add_and_connect(circuit, name+'~or', 'OR2', None, None, outs[0])
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Line(circuit, n_and0, n_or)
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Line(circuit, n_and1, n_or)
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elif n.kind.startswith('AOI22X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n_and1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n_nor = add_and_connect(circuit, name+'~nor', 'NOR2', None, None, outs[0])
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Line(circuit, n_and0, n_nor)
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Line(circuit, n_and1, n_nor)
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elif n.kind.startswith('AO221X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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@@ -104,6 +122,15 @@ def split_complex_gates(circuit):
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Line(circuit, n_or0, n_and0)
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Line(circuit, n_or1, n_and0)
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Line(circuit, n_and0, n_and1)
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elif n.kind.startswith('OAI221X'):
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n.remove()
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n_or0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n_or1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', None, None, None)
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n_nand1 = add_and_connect(circuit, name+'~nand1', 'NAND2', None, ins[4], outs[0])
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Line(circuit, n_or0, n_and0)
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Line(circuit, n_or1, n_and0)
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Line(circuit, n_and0, n_nand1)
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elif n.kind.startswith('AO222X'):
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n.remove()
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n_and0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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@@ -137,11 +164,75 @@ def split_complex_gates(circuit):
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Line(circuit, n_or1, n_and0)
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Line(circuit, n_or2, n_and1)
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Line(circuit, n_and0, n_and1)
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elif n.kind.startswith('OAI222X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n2 = add_and_connect(circuit, name+'~or2', 'OR2', ins[4], ins[5], None)
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n3 = add_and_connect(circuit, name+'~and0', 'AND2', None, None, None)
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n4 = add_and_connect(circuit, name+'~nand1', 'NAND2', None, None, outs[0])
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Line(circuit, n0, n3)
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Line(circuit, n1, n3)
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Line(circuit, n2, n4)
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Line(circuit, n3, n4)
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elif n.kind.startswith('AND3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~and1', 'AND2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('OR3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~or1', 'OR2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('XOR3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~xor0', 'XOR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~xor1', 'XOR2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('NAND3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~and', 'AND2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~nand', 'NAND2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('NOR3X'):
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n.remove()
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n_or = add_and_connect(circuit, name+'~or', 'OR2', ins[0], ins[1], None)
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n_nor = add_and_connect(circuit, name+'~nor', 'NOR2', None, ins[2], outs[0])
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Line(circuit, n_or, n_nor)
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n0 = add_and_connect(circuit, name+'~or', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~nor', 'NOR2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('XNOR3X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~xor', 'XOR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~xnor', 'XNOR2', None, ins[2], outs[0])
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Line(circuit, n0, n1)
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elif n.kind.startswith('AND4X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n2 = add_and_connect(circuit, name+'~and2', 'AND2', None, None, outs[0])
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Line(circuit, n0, n2)
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Line(circuit, n1, n2)
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elif n.kind.startswith('OR4X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n2 = add_and_connect(circuit, name+'~or2', 'OR2', None, None, outs[0])
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Line(circuit, n0, n2)
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Line(circuit, n1, n2)
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elif n.kind.startswith('NAND4X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~and0', 'AND2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~and1', 'AND2', ins[2], ins[3], None)
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n2 = add_and_connect(circuit, name+'~nand2', 'NAND2', None, None, outs[0])
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Line(circuit, n0, n2)
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Line(circuit, n1, n2)
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elif n.kind.startswith('NOR4X'):
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n.remove()
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n0 = add_and_connect(circuit, name+'~or0', 'OR2', ins[0], ins[1], None)
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n1 = add_and_connect(circuit, name+'~or1', 'OR2', ins[2], ins[3], None)
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n2 = add_and_connect(circuit, name+'~nor2', 'NOR2', None, None, outs[0])
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Line(circuit, n0, n2)
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Line(circuit, n1, n2)
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elif n.kind.startswith('FADDX'):
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n.remove()
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# forks for fan-outs
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@@ -169,6 +260,17 @@ def split_complex_gates(circuit):
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n_or = add_and_connect(circuit, name + '~or0', 'OR2', None, None, outs[1])
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Line(circuit, n_and0, n_or)
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Line(circuit, n_and1, n_or)
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elif n.kind.startswith('HADDX'):
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n.remove()
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# forks for fan-outs
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f_a = add_and_connect(circuit, name + '~fork0', '__fork__', ins[0])
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f_b = add_and_connect(circuit, name + '~fork1', '__fork__', ins[1])
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n_xor0 = add_and_connect(circuit, name + '~xor0', 'XOR2', None, None, outs[1])
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Line(circuit, f_a, n_xor0)
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Line(circuit, f_b, n_xor0)
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n_and0 = add_and_connect(circuit, name + '~and0', 'AND2', None, None, outs[0])
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Line(circuit, f_a, n_and0)
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Line(circuit, f_b, n_and0)
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elif n.kind.startswith('MUX21X'):
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n.remove()
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f_s = add_and_connect(circuit, name + '~fork0', '__fork__', ins[2])
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@@ -181,5 +283,7 @@ def split_complex_gates(circuit):
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Line(circuit, f_s, n_and1)
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Line(circuit, n_and0, n_or0)
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Line(circuit, n_and1, n_or0)
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elif n.kind.startswith('DFFSSR'):
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n.kind = 'DFFX1'
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n_and0 = add_and_connect(circuit, name + '~and0', 'AND2', ins[0], ins[2], None)
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Line(circuit, n_and0, (n, 0))
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+1
-1
@@ -170,7 +170,7 @@ class SdfTransformer(Transformer):
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return DelayFile(name, cells)
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def parse(sdf) -> DelayFile:
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def parse(sdf):
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grammar = r"""
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start: "(DELAYFILE" ( "(SDFVERSION" _NOB ")"
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| "(DESIGN" "\"" NAME "\"" ")"
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+16
-4
@@ -1,6 +1,8 @@
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from lark import Lark, Transformer
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from collections import namedtuple
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import gzip
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from lark import Lark, Transformer
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from .circuit import Circuit, Node, Line
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from .saed import pin_index, pin_is_output
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@@ -110,7 +112,7 @@ class VerilogTransformer(Transformer):
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Line(c, Node(c, const, const), Node(c, s))
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fork = c.forks[s]
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if self.branchforks:
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branchfork = Node(c, fork.name + "~" + n.name)
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branchfork = Node(c, fork.name + "~" + n.name + "/" + p)
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Line(c, fork, branchfork)
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fork = branchfork
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Line(c, fork, (n, pin_index(stmt.type, p)))
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@@ -128,7 +130,6 @@ class VerilogTransformer(Transformer):
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return args
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def parse(verilog, branchforks=False) -> Circuit:
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grammar = """
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start: (module)*
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module: "module" name parameters ";" (_statement)* "endmodule"
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@@ -149,6 +150,17 @@ def parse(verilog, branchforks=False) -> Circuit:
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%ignore ( /\\r?\\n/ | COMMENT )+
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%ignore /[\\t \\f]+/
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"""
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def loads(s, *, branchforks=False):
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return Lark(grammar, parser="lalr", transformer=VerilogTransformer(branchforks)).parse(s)
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def load(fp, *, branchforks=False):
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return loads(fp.read(), branchforks=branchforks)
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def parse(verilog, branchforks=False):
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if '\n' not in str(verilog): # One line?: Assuming it is a file name.
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if str(verilog).endswith('.gz'):
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with gzip.open(verilog, 'rt') as f:
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@@ -158,4 +170,4 @@ def parse(verilog, branchforks=False) -> Circuit:
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text = f.read()
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else:
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text = str(verilog)
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return Lark(grammar, parser="lalr", transformer=VerilogTransformer(branchforks)).parse(text)
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return loads(text, branchforks=branchforks)
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