for release 0.0.4

- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements

.gitignore

@@ -1,10 +1,12 @@
-**/__pycache__
-**/.ipynb_checkpoints
-**/.pytest_cache
-**/.DS_Store
-**/*.pyc
+__pycache__
+.ipynb_checkpoints
+.pytest_cache
+.DS_Store
+*.pyc
 docs/_build
 build
 dist
 .idea
+.vscode
 src/kyupy.egg-info
+*nogit*