fixups for empty standard cells

src/kyupy/circuit.py

@@ -448,7 +448,7 @@ class Circuit:
                     node_map[n] = Node(self, f'{node.name}~{n.name}', n.kind)
             elif len(n.outs) > 0 and len(n.ins) > 0:  # output is also read by impl. circuit, need to add a fork.
                 node_map[n] = Node(self, f'{node.name}~{n.name}')
-            elif len(n.ins) == 0 and len(n.outs) > 1:  # input is read by multiple nodes, need to add fork.
+            elif len(n.ins) == 0 and len(n.outs) != 1:  # input is read by multiple nodes (or no nodes), need to add fork.
                 node_map[n] = Node(self, f'{node.name}~{n.name}')
         for l in impl.lines:  # add all internal lines to main circuit
             if l.reader in node_map and l.driver in node_map:

src/kyupy/verilog.py

@@ -52,6 +52,7 @@ class VerilogTransformer(Transformer):
     @staticmethod
     def instantiation(args):
         pinmap = {}
+        if args[2] is not None:
             for idx, pin in enumerate(args[2:]):
                 p = pin.children[0]
                 if isinstance(p, tuple):  # named pin