A python module for parsing, processing, and simulating gate-level circuits.
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import pytest
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@pytest.fixture(scope='session')
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def mydir():
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import os
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from pathlib import Path
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return Path(os.path.realpath(os.path.join(os.getcwd(), os.path.dirname(__file__))))
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@pytest.fixture(scope='session')
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def b14_circuit(mydir):
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from kyupy import verilog
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from kyupy.techlib import SAED32
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return verilog.load(mydir / 'b14.v.gz', branchforks=True, tlib=SAED32)
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@pytest.fixture(scope='session')
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def b14_delays(mydir, b14_circuit):
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from kyupy import sdf
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from kyupy.techlib import SAED32
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return sdf.load(mydir / 'b14.sdf.gz').iopaths(b14_circuit, tlib=SAED32)[1:2]
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