In-Field Testing Using MISR

Research code for investigations of Silent Data Corruptions (SDCs) caused by hardware faults.

Quick Start

This project has submodules. To ensure everything is up-to-date, run the following after git clone, git pull or git checkout:

git submodule init
git submodule sync
git submodule update

This project manages reproducible programming environments with:

• uv for managing python environments.
• nix for managing non-python tools and benchmark designs. Follow this guide or this guide to setup nix-eda binary cache to avoid re-building EDA-related tools.

Usage

To access non-Python tools such as iverilog, run nix develop before any of the commands below to enter the appropriate shell environment. Commands that only rely on Python tools work also outside a nix develop shell if uv is installed on the base system.

JPEG

Compile jpeg decoder core using iverilog and run RTL simulation of the jpeg decoder core using vvp:

make
uv run jpeg_core_tb_run_plasma.py

See uv run jpeg_core_tb_run_plasma.py --help for more options.

PicoRV32

Run picorv32's built-in testbenches (generate picorv32/testbench.vcd) with one of these commands:

make test_vcd
make test_ez_vcd

Import generated VCD with kyupy and convert it to a pattern file for later fault simulation:

uv run picorv32_vcd_import.py picorv32/testbench.vcd patterns.npy

See uv run picorv32_vcd_import.py --help for more options.

Other Benchmark Circuits

Load synthesized circuits and display statistics (example code):

uv run load_sky130_circuits.py

This script demonstrates how to obtain synthesized netlists via nix derivations published in this github repository. These circuits along with layout and timings are built on-demand using LibreLane classic flow if not yet available in local nix store.

To access the full design data (netlist, timing, layout, ...), call one of these:

nix build github:s-holst/benchmark-circuits#picorv32-sky130
nix build github:s-holst/benchmark-circuits#jpeg_core-sky130