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#!/usr/bin/env -S uv run |
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import re |
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import argparse |
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import numpy as np |
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from PIL import Image |
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from kyupy import verilog, vcd, log, logic |
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from kyupy.techlib import SKY130 |
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from kyupy.logic_sim import LogicSim4V |
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def check_conflicts(patterns1, patterns2, names): |
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conflicts = (patterns1 != patterns2) & (patterns1 != logic.UNKNOWN) & (patterns1 != logic.UNASSIGNED) & (patterns2 != logic.UNKNOWN) & (patterns2 != logic.UNASSIGNED) |
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if conflicts.sum() > 0: |
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for pat_idx in range(patterns1.shape[1]): |
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for c, p1, p2, n in zip(conflicts[:,pat_idx], patterns1[:,pat_idx], patterns2[:,pat_idx], names): |
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if c: |
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log.error(f'incompatible logic values: pattern: {pat_idx} (p)pio: {n} {p1} != {p2}') |
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assert conflicts.sum() == 0, "incompatible patterns" |
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def propagate_and_check(sim: LogicSim4V, patterns: np.ndarray, node2name: dict): |
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responses = np.full_like(patterns, logic.UNASSIGNED) |
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sim.simulate(patterns, responses) |
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#to_image(np.concatenate([patterns, responses]), 'pat_res.png') |
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po_names = [node2name[sim.circuit.s_nodes[loc]] for loc in sim.po_s_locs] |
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ppio_names = [node2name[sim.circuit.s_nodes[loc]] for loc in sim.ppio_s_locs] |
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merged = np.full_like(patterns, logic.UNASSIGNED) |
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merged[sim.pi_s_locs] = patterns[sim.pi_s_locs] # copy primary inputs |
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merged[sim.po_s_locs] = logic.mv_merge(patterns[sim.po_s_locs], responses[sim.po_s_locs]) # merge primary outputs |
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merged[sim.ppio_s_locs,0] = patterns[sim.ppio_s_locs,0] # copy pseudo-primary io for very first clock cycle (simulation does not give these) |
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merged[sim.ppio_s_locs,1:] = logic.mv_merge(patterns[sim.ppio_s_locs,1:], responses[sim.ppio_s_locs,:-1]) # merge pseudo-primary io, shifted by one clock cycle (discard ppio of very last clock cycle from sim) |
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check_conflicts(patterns[sim.po_s_locs], responses[sim.po_s_locs], po_names) |
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check_conflicts(patterns[sim.ppio_s_locs,1:], responses[sim.ppio_s_locs,:-1], ppio_names) |
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return merged |
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def to_image(data: np.ndarray, path: str): |
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_palette = np.full(8, 128, dtype=np.uint8) |
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_palette[0] = 0 # black |
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_palette[3] = 255 # white |
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pixels = _palette[data] |
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Image.fromarray(pixels, mode='L').save(path) |
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def find_name(c, n): |
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for nn in c.fanout([n], node_filter=lambda n: n.kind in ('input', 'BUF1', '__fork__', 'DFF')): |
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if nn.name[0] == '_': continue |
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if nn.name.startswith('net'): continue |
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if nn.name.startswith('fanout'): continue |
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if nn.name.startswith('hold'): continue |
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if nn.name.startswith('output'): continue |
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if nn.name.startswith('load_slew'): continue |
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if nn.name.startswith('max_cap'): continue |
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if nn.name.startswith('output'): continue |
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if nn.name.startswith('wire'): continue |
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if nn.name.startswith('ANTENNA'): continue |
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return nn.name |
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return n.name |
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def main(): |
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parser = argparse.ArgumentParser() |
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parser.add_argument('dut', type=str, help='verilog file with unit under test (uut)') |
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parser.add_argument('vcd', type=str, help='vcd file to process') |
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args = parser.parse_args() |
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c = verilog.load(args.dut, tlib=SKY130) |
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log.info(f'circuit: {c}') |
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c.resolve_tlib_cells(tlib=SKY130) |
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s_locs = {} #{n.name: l for l, n in enumerate(c.s_nodes)} |
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name2node = {} |
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node2name = {} |
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for l, n in enumerate(c.s_nodes): |
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name = find_name(c, n) |
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s_locs[name] = l |
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name2node[name] = n |
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node2name[n] = name |
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clk_loc = next(s_locs[name] for name in ['blif_clk_net', 'clk'] if name in s_locs) |
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s_found: list[str|None] = [None] * len(c.s_nodes) |
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def var_assign(var: vcd.Var, name: str): |
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if var.width == 1: |
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s_found[s_locs[name]] = name |
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return [s_locs[name]] |
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else: |
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locs = [] |
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for i in reversed(range(var.width)): |
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if loc := s_locs.get(f'{name}[{i}]'): |
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s_found[loc] = f'{name}[{i}]' |
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locs.append(loc) |
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else: |
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locs.append(-1) |
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return locs |
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def var_locs_picorv(var: vcd.Var): |
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if var.scope.name in ['uut', 'picorv32_core', 'pcpi_mul', 'pcpi_div']: |
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if var.reference.startswith('cpu_state'): # FSM got re-coded during synthesis |
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return [] |
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elif var.reference.startswith('mem_wordsize'): # FSM got re-coded during synthesis |
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return [] |
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elif var.reference.startswith('dbg_reg_x'): |
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name = re.sub(r'dbg_reg_x([0-9]+)', r'cpuregs[\1]', var.reference) |
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elif var.scope.name == 'pcpi_mul': |
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name = 'genblk1.genblk1.pcpi_mul.' + var.reference |
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elif var.scope.name == 'pcpi_div': |
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name = 'genblk2.pcpi_div.' + var.reference |
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else: |
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name = var.reference |
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if name in s_locs: |
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return var_assign(var, name) |
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elif var.width > 1: |
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if ' ' not in name: return [] |
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name, indices = name.split() |
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assert indices == f'[{var.width-1}:0]', f'unsupported indices: {var.reference}' |
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return var_assign(var, name) |
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return [] |
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def step_filter(time, values, var_map): |
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clk_val = values[clk_loc] |
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return clk_val == 0 and time < 100e6 |
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sim = LogicSim4V(c, sims=1024) |
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log.info(f'sim: {sim}') |
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v = vcd.load(args.vcd, var_locs=var_locs_picorv, step_filter=step_filter, s_len=sim.s_len) |
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log.info(f'vcd: {v}') |
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unknown_pi = 0 |
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unknown_ppio = 0 |
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for l, n in enumerate(sim.circuit.s_nodes): |
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if n.kind == 'output': continue |
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if 'cpu_state' in node2name[n] or 'mem_wordsize' in node2name[n]: continue # re-coded FSMs |
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if s_found[l] is None: |
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log.warn(f'No VCD $var found for netlist port loc: {l} name: {node2name[n]} node: {n}') |
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if n.kind == 'input': |
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unknown_pi += 1 |
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else: |
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unknown_ppio += 1 |
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log.info(f'Unassigned PI: {unknown_pi}/{len(sim.pi_s_locs)} PPIO: {unknown_ppio}/{len(sim.ppio_s_locs)}') |
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log.info(f'Total bits unassigned: {(v.data == logic.UNASSIGNED).sum()} unknown: {(v.data == logic.UNKNOWN).sum()}') |
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merged = v.data |
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np.save('testbench_orig.npy', merged) |
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for i in range(30): |
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merged = propagate_and_check(sim, merged, node2name) |
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log.info(f'PropCycle[{i}] total bits unassigned: {(merged == logic.UNASSIGNED).sum()} unknown: {(merged == logic.UNKNOWN).sum()}') |
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np.save('testbench_prop.npy', merged) |
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if __name__ == "__main__": |
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main() |
