better docs and vscode config

This commit is contained in:
stefan committed 2026-05-02 23:28:13 +09:00
1 parent 8b94c5a15f
commit 048d23bc1a
3 files changed
+18 -5

No files matched your search

+4
View File
@@ -0,0 +1,4 @@
{
"python.defaultInterpreterPath": "${workspaceFolder}/.venv/bin/python",
"python.analysis.extraPaths": ["${workspaceFolder}/kyupy/src"]
}
+9 -1
View File
@@ -13,7 +13,7 @@ This project uses [Nix](https://nixos.org) to manage reproducible programming en
Run `nix develop` to enter a shell with all necessary software.
If `nix` is not installed, follow this [guide](https://librelane.readthedocs.io/en/stable/installation/nix_installation/index.html). No need to clone `librelane` here, but it is good to set up the `extra-substituters` as described in the guide for using LibreLane in the future (for making layouts with SkyWater 130nm technology).
If `nix` is not installed, follow this [guide](https://librelane.readthedocs.io/en/stable/installation/nix_installation/index.html). No need to clone `librelane` here, but it is good to set up the `extra-substituters` as described in the guide for using LibreLane for making layouts with SkyWater 130nm technology.
## Usage
@@ -25,3 +25,11 @@ make
uv run jpeg_core_tb_run_plasma.py
```
Load synthesized circuits and display statistics (example code):
```
uv run load_sky130_circuits.py
```
Works also outside a `nix develop` shell if [uv](https://docs.astral.sh/uv/) is installed on the base system. The script demonstrates how to obtain synthesized netlists via nix derivations [published in this github repository](https://github.com/s-holst/benchmark-circuits). These circuits along with layout and timings are built on-demand (using LibreLane) if not yet available in local nix store.
+5 -4
View File
@@ -15,10 +15,11 @@ def path_for(circuit: str):
def verilog_nl_path_for(circuit: str):
return next(path_for(circuit).glob("*/nl/*.nl.v"))
def main():
c = verilog.load(verilog_nl_path_for("picorv32-sky130"), tlib=SKY130)
def print_circuit_stats(circuit: str):
print(circuit)
c = verilog.load(verilog_nl_path_for(circuit), tlib=SKY130)
c.resolve_tlib_cells(SKY130)
for kind, count in sorted(c.stats.items()): print(f'{kind:10s} {count}')
for kind, count in sorted(c.stats.items()): print(f' {kind:10s} {count}')
if __name__ == "__main__":
main()
print_circuit_stats("picorv32-sky130")