better docs and vscode config
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@@ -0,0 +1,4 @@
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{
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"python.defaultInterpreterPath": "${workspaceFolder}/.venv/bin/python",
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"python.analysis.extraPaths": ["${workspaceFolder}/kyupy/src"]
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}
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@@ -13,7 +13,7 @@ This project uses [Nix](https://nixos.org) to manage reproducible programming en
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Run `nix develop` to enter a shell with all necessary software.
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Run `nix develop` to enter a shell with all necessary software.
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If `nix` is not installed, follow this [guide](https://librelane.readthedocs.io/en/stable/installation/nix_installation/index.html). No need to clone `librelane` here, but it is good to set up the `extra-substituters` as described in the guide for using LibreLane in the future (for making layouts with SkyWater 130nm technology).
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If `nix` is not installed, follow this [guide](https://librelane.readthedocs.io/en/stable/installation/nix_installation/index.html). No need to clone `librelane` here, but it is good to set up the `extra-substituters` as described in the guide for using LibreLane for making layouts with SkyWater 130nm technology.
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## Usage
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## Usage
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@@ -25,3 +25,11 @@ make
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uv run jpeg_core_tb_run_plasma.py
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uv run jpeg_core_tb_run_plasma.py
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```
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```
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Load synthesized circuits and display statistics (example code):
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```
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uv run load_sky130_circuits.py
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```
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Works also outside a `nix develop` shell if [uv](https://docs.astral.sh/uv/) is installed on the base system. The script demonstrates how to obtain synthesized netlists via nix derivations [published in this github repository](https://github.com/s-holst/benchmark-circuits). These circuits along with layout and timings are built on-demand (using LibreLane) if not yet available in local nix store.
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@@ -15,10 +15,11 @@ def path_for(circuit: str):
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def verilog_nl_path_for(circuit: str):
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def verilog_nl_path_for(circuit: str):
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return next(path_for(circuit).glob("*/nl/*.nl.v"))
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return next(path_for(circuit).glob("*/nl/*.nl.v"))
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def main():
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def print_circuit_stats(circuit: str):
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c = verilog.load(verilog_nl_path_for("picorv32-sky130"), tlib=SKY130)
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print(circuit)
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c = verilog.load(verilog_nl_path_for(circuit), tlib=SKY130)
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c.resolve_tlib_cells(SKY130)
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c.resolve_tlib_cells(SKY130)
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for kind, count in sorted(c.stats.items()): print(f'{kind:10s} {count}')
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for kind, count in sorted(c.stats.items()): print(f' {kind:10s} {count}')
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if __name__ == "__main__":
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if __name__ == "__main__":
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main()
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print_circuit_stats("picorv32-sky130")
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