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29 lines
1.1 KiB
29 lines
1.1 KiB
from kyupy import bench |
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from kyupy.techlib import KYUPY |
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from fsim.static import LineRoles |
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def test_trivial_inv(): |
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c = bench.parse('input(i) output(o) o=INV(i)') |
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lr = LineRoles(c, KYUPY) |
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assert len(lr.line2roles) == 2 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 2 |
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def test_input_fanout(): |
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c = bench.parse('input(i) output(o1) output(o2) o1=INV(i) o2=INV(i)') |
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lr = LineRoles(c, KYUPY) |
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assert len(lr.line2roles) == 4 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 4 |
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def test_fanout(): |
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c = bench.parse('input(i) output(o1) output(o2) ii=INV(i) o1=INV(ii) o2=INV(ii)') |
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lr = LineRoles(c, KYUPY) |
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assert len(lr.line2roles) == 6 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 6 |
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def test_s27(s27_bench): |
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lr = LineRoles(s27_bench, KYUPY) |
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assert len(lr.line2roles) == 34 # total number of signal lines in circuit |
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# 2 + 9 + 23 = 34 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT]) == 2 |
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assert len(lr.roles2lines[LineRoles.LOGIC_SEQ]) == 9 |
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assert len(lr.roles2lines[LineRoles.LOGIC_OUT|LineRoles.LOGIC_SEQ]) == 23
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