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synthesized fma packages

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stefan committed 2026-05-28 08:37:26 +09:00
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.gitignore
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result
.python-version
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3.14
README.md
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Machine Learning Hardware Modules
=================================
Collection of various hardware components used for machine learning accelerator research.
flake.lock
Generated
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{
"nodes": {
"benchmark-circuits": {
"inputs": {
"librelane": "librelane",
"nixpkgs": "nixpkgs_2"
},
"locked": {
"lastModified": 1779683213,
"narHash": "sha256-4VTmok0G04LHmz/gOw1D6/NJHW4gq85YGKEuPr1RgeM=",
"owner": "s-holst",
"repo": "benchmark-circuits",
"rev": "72f22e850f97252a8ae84b0f76a6f9472f74de38",
"type": "github"
},
"original": {
"owner": "s-holst",
"repo": "benchmark-circuits",
"type": "github"
}
},
"ciel": {
"inputs": {
"nix-eda": [
"benchmark-circuits",
"librelane",
"nix-eda"
]
},
"locked": {
"lastModified": 1764091696,
"narHash": "sha256-AWbkHL0zO3tD0mE3dZIcj8mVND7o3imTxOpEfOtlRDI=",
"owner": "fossi-foundation",
"repo": "ciel",
"rev": "afcb23d368614ffa1e7e96584ed33f839c71c576",
"type": "github"
},
"original": {
"owner": "fossi-foundation",
"repo": "ciel",
"type": "github"
}
},
"ciel_2": {
"inputs": {
"nix-eda": [
"librelane",
"nix-eda"
]
},
"locked": {
"lastModified": 1764091696,
"narHash": "sha256-AWbkHL0zO3tD0mE3dZIcj8mVND7o3imTxOpEfOtlRDI=",
"owner": "fossi-foundation",
"repo": "ciel",
"rev": "afcb23d368614ffa1e7e96584ed33f839c71c576",
"type": "github"
},
"original": {
"owner": "fossi-foundation",
"repo": "ciel",
"type": "github"
}
},
"cvfpu-src": {
"flake": false,
"locked": {
"lastModified": 1778159595,
"narHash": "sha256-GV8i3+GgsshXVTRrivl9EmTWupzckVWE4DiYBuyD1fs=",
"ref": "refs/heads/develop",
"rev": "106251e502747f17d931a20db0bdbab9e1a6c2ff",
"revCount": 304,
"submodules": true,
"type": "git",
"url": "https://github.com/openhwgroup/cvfpu.git"
},
"original": {
"submodules": true,
"type": "git",
"url": "https://github.com/openhwgroup/cvfpu.git"
}
},
"devshell": {
"inputs": {
"nixpkgs": [
"benchmark-circuits",
"librelane",
"nix-eda",
"nixpkgs"
]
},
"locked": {
"lastModified": 1768818222,
"narHash": "sha256-460jc0+CZfyaO8+w8JNtlClB2n4ui1RbHfPTLkpwhU8=",
"owner": "numtide",
"repo": "devshell",
"rev": "255a2b1725a20d060f566e4755dbf571bbbb5f76",
"type": "github"
},
"original": {
"owner": "numtide",
"repo": "devshell",
"type": "github"
}
},
"devshell_2": {
"inputs": {
"nixpkgs": [
"librelane",
"nix-eda",
"nixpkgs"
]
},
"locked": {
"lastModified": 1768818222,
"narHash": "sha256-460jc0+CZfyaO8+w8JNtlClB2n4ui1RbHfPTLkpwhU8=",
"owner": "numtide",
"repo": "devshell",
"rev": "255a2b1725a20d060f566e4755dbf571bbbb5f76",
"type": "github"
},
"original": {
"owner": "numtide",
"repo": "devshell",
"type": "github"
}
},
"flake-compat": {
"locked": {
"lastModified": 1733328505,
"narHash": "sha256-NeCCThCEP3eCl2l/+27kNNK7QrwZB1IJCrXfrbv5oqU=",
"rev": "ff81ac966bb2cae68946d5ed5fc4994f96d0ffec",
"revCount": 69,
"type": "tarball",
"url": "https://api.flakehub.com/f/pinned/edolstra/flake-compat/1.1.0/01948eb7-9cba-704f-bbf3-3fa956735b52/source.tar.gz"
},
"original": {
"type": "tarball",
"url": "https://flakehub.com/f/edolstra/flake-compat/1.tar.gz"
}
},
"flake-compat_2": {
"locked": {
"lastModified": 1733328505,
"narHash": "sha256-NeCCThCEP3eCl2l/+27kNNK7QrwZB1IJCrXfrbv5oqU=",
"rev": "ff81ac966bb2cae68946d5ed5fc4994f96d0ffec",
"revCount": 69,
"type": "tarball",
"url": "https://api.flakehub.com/f/pinned/edolstra/flake-compat/1.1.0/01948eb7-9cba-704f-bbf3-3fa956735b52/source.tar.gz"
},
"original": {
"type": "tarball",
"url": "https://flakehub.com/f/edolstra/flake-compat/1.tar.gz"
}
},
"librelane": {
"inputs": {
"ciel": "ciel",
"devshell": "devshell",
"flake-compat": "flake-compat",
"nix-eda": "nix-eda"
},
"locked": {
"lastModified": 1775150546,
"narHash": "sha256-JxWuaOBhkjjw4sp7l++QF+0EzGIhPAOaJcKwwmdTg+w=",
"owner": "librelane",
"repo": "librelane",
"rev": "c82049f0234a49bbf72ebcc89539529f31d8997e",
"type": "github"
},
"original": {
"owner": "librelane",
"ref": "3.0.2",
"repo": "librelane",
"type": "github"
}
},
"librelane_2": {
"inputs": {
"ciel": "ciel_2",
"devshell": "devshell_2",
"flake-compat": "flake-compat_2",
"nix-eda": "nix-eda_2"
},
"locked": {
"lastModified": 1775150546,
"narHash": "sha256-JxWuaOBhkjjw4sp7l++QF+0EzGIhPAOaJcKwwmdTg+w=",
"owner": "librelane",
"repo": "librelane",
"rev": "c82049f0234a49bbf72ebcc89539529f31d8997e",
"type": "github"
},
"original": {
"owner": "librelane",
"ref": "3.0.2",
"repo": "librelane",
"type": "github"
}
},
"nix-eda": {
"inputs": {
"nixpkgs": "nixpkgs"
},
"locked": {
"lastModified": 1773918136,
"narHash": "sha256-nSKBMGP8/ZC7qB3Lzd+FwM8REqOxlh8wpYDf2hlK6Gg=",
"owner": "fossi-foundation",
"repo": "nix-eda",
"rev": "8f990fb77529c09e540e453cd836af9930ec58db",
"type": "github"
},
"original": {
"owner": "fossi-foundation",
"ref": "6.11.0",
"repo": "nix-eda",
"type": "github"
}
},
"nix-eda_2": {
"inputs": {
"nixpkgs": "nixpkgs_3"
},
"locked": {
"lastModified": 1773918136,
"narHash": "sha256-nSKBMGP8/ZC7qB3Lzd+FwM8REqOxlh8wpYDf2hlK6Gg=",
"owner": "fossi-foundation",
"repo": "nix-eda",
"rev": "8f990fb77529c09e540e453cd836af9930ec58db",
"type": "github"
},
"original": {
"owner": "fossi-foundation",
"ref": "6.11.0",
"repo": "nix-eda",
"type": "github"
}
},
"nixpkgs": {
"locked": {
"lastModified": 1766201043,
"narHash": "sha256-eplAP+rorKKd0gNjV3rA6+0WMzb1X1i16F5m5pASnjA=",
"owner": "nixos",
"repo": "nixpkgs",
"rev": "b3aad468604d3e488d627c0b43984eb60e75e782",
"type": "github"
},
"original": {
"owner": "nixos",
"ref": "nixos-25.11",
"repo": "nixpkgs",
"type": "github"
}
},
"nixpkgs_2": {
"locked": {
"lastModified": 1777268161,
"narHash": "sha256-bxrdOn8SCOv8tN4JbTF/TXq7kjo9ag4M+C8yzzIRYbE=",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "1c3fe55ad329cbcb28471bb30f05c9827f724c76",
"type": "github"
},
"original": {
"owner": "NixOS",
"ref": "nixos-unstable",
"repo": "nixpkgs",
"type": "github"
}
},
"nixpkgs_3": {
"locked": {
"lastModified": 1766201043,
"narHash": "sha256-eplAP+rorKKd0gNjV3rA6+0WMzb1X1i16F5m5pASnjA=",
"owner": "nixos",
"repo": "nixpkgs",
"rev": "b3aad468604d3e488d627c0b43984eb60e75e782",
"type": "github"
},
"original": {
"owner": "nixos",
"ref": "nixos-25.11",
"repo": "nixpkgs",
"type": "github"
}
},
"nixpkgs_4": {
"locked": {
"lastModified": 1779508470,
"narHash": "sha256-Ap9KJX+5xHIn3bPIpfNgT6MEXdAECECwo4/rmlQD74M=",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "29916453413845e54a65b8a1cf996842300cd299",
"type": "github"
},
"original": {
"owner": "NixOS",
"ref": "nixos-unstable",
"repo": "nixpkgs",
"type": "github"
}
},
"root": {
"inputs": {
"benchmark-circuits": "benchmark-circuits",
"cvfpu-src": "cvfpu-src",
"librelane": "librelane_2",
"nixpkgs": "nixpkgs_4",
"sv2v-src": "sv2v-src"
}
},
"sv2v-src": {
"flake": false,
"locked": {
"lastModified": 1774651589,
"narHash": "sha256-ziwLw1/S4wbnqml/AnN/yerOJJ3VOfRc3dZa8cmEaD0=",
"owner": "zachjs",
"repo": "sv2v",
"rev": "6662fa5da71f87797598060f17728b284b99a9fc",
"type": "github"
},
"original": {
"owner": "zachjs",
"repo": "sv2v",
"type": "github"
}
}
},
"root": "root",
"version": 7
}
flake.nix
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{
description = "Packages for synthesizing machine learning hardware modules";
inputs = {
nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
librelane.url = "github:librelane/librelane/3.0.2";
benchmark-circuits.url = "github:s-holst/benchmark-circuits";
sv2v-src = {
url = "github:zachjs/sv2v";
flake = false;
};
cvfpu-src = {
url = "git+https://github.com/openhwgroup/cvfpu.git?submodules=1";
flake = false;
};
};
outputs = { self, nixpkgs, librelane, benchmark-circuits, sv2v-src, cvfpu-src }:
let
systems = [ "x86_64-linux" "aarch64-linux" "x86_64-darwin" "aarch64-darwin" ];
forAllSystems = nixpkgs.lib.genAttrs systems;
in {
packages = forAllSystems (system:
let
pkgs = nixpkgs.legacyPackages.${system};
librelane-pkg = librelane.packages.${system}.default;
gsclib = benchmark-circuits.packages.${system}.iwls-gsclib;
sky130-pdk = benchmark-circuits.packages.${system}.sky130-pdk;
sv2v = pkgs.haskell.lib.compose.justStaticExecutables (pkgs.haskell.packages.ghc910.callCabal2nix "sv2v" sv2v-src { });
run-sv2v = {data_width}:
''
sed -e 's/default disable iff/\/\/default disable iff/' <$src/src/common_cells/src/rr_arb_tree.sv >rr_arb_tree_patched.sv
sv2v \
-I$src/src/common_cells/include \
$src/src/common_cells/src/cf_math_pkg.sv \
$src/src/common_cells/src/lzc.sv \
rr_arb_tree_patched.sv \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v \
$src/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ctrl.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_double.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ff1.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_pack.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_prepare.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_round.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_scalar_dp.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_bound_table.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_with_sqrt.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v \
$src/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_top.v \
$src/src/fpnew_pkg.sv \
$src/src/fpnew_cast_multi.sv \
$src/src/fpnew_divsqrt_th_64_multi.sv \
$src/src/fpnew_opgroup_multifmt_slice.sv \
$src/src/fpnew_noncomp.sv \
$src/src/fpnew_rounding.sv \
$src/src/fpnew_classifier.sv \
$src/src/fpnew_fma.sv \
$srcExtra/fma_float${toString data_width}.sv | sed -e 's/\$finish/\/\/\$finish/; s/\(initial \)*\$display/\/\/\$display/' > top.v
'';
run-yosys = {verilog_file ? "top.v", data_width ? 0, sum_width ? 0}:
''
yosys <<EOF >out.log 2>&1
# Read design
read_verilog ${verilog_file}
hierarchy -check -top top ''
+ (if data_width > 0 then "-chparam DATA_WIDTH ${toString data_width}" else "")
+ (if sum_width > 0 then "-chparam SUM_WIDTH ${toString sum_width}" else "")
+ ''
# Coarse-grain synthesis
flatten; proc; memory; opt;
fsm; opt; # FSM pass re-codes states
wreduce; opt;
splitnets; opt;
# Technology mapping
techmap; opt; clean;
dfflibmap -liberty ${gsclib}/GSCLib_3.0.lib
abc -liberty ${gsclib}/GSCLib_3.0.lib
opt_clean
# Write netlist
write_verilog -noattr nl.v
EOF
'';
run-librelane = {verilog_file ? "top.v", data_width ? 0, sum_width ? 0, clock_period ? 20}:
''
mkdir top
cat > top/config.yaml << EOF
DESIGN_NAME: top
''
+ (if data_width > 0 then "SYNTH_PARAMETERS: [ 'DATA_WIDTH=${toString data_width}' "
+ (if sum_width > 0 then ", 'SUM_WIDTH=${toString sum_width}' ]\n" else "]\n") else "") +
''
VERILOG_FILES: [ ${verilog_file} ]
CLOCK_PERIOD: ${toString clock_period}
EOF
cat top/config.yaml
librelane --manual-pdk --pdk-root ${sky130-pdk} --run-tag run top/config.yaml
'';
mk_fma_fixed_gsclib = {data_width, sum_width}: pkgs.stdenv.mkDerivation {
name = "fma_fixed_${toString data_width}_${toString sum_width}_gsclib";
src = ./.;
unpackPhase = "true";
buildPhase = run-yosys { verilog_file = "$src/fma_fixed.v"; inherit data_width; inherit sum_width; };
installPhase =
''
ODIR=fma_fixed_${toString data_width}_${toString sum_width}_gsclib
mkdir -p $out/$ODIR/{log,nl}
cp out.log $out/$ODIR/log/top.log
cp nl.v $out/$ODIR/nl/top.nl.v
'';
buildInputs = [ pkgs.yosys ];
};
mk_fma_float_gsclib = {data_width}: pkgs.stdenv.mkDerivation {
name = "fma_float_${toString data_width}_gsclib";
src = cvfpu-src;
srcExtra = ./.;
unpackPhase = "true";
buildPhase = run-sv2v {inherit data_width;} + run-yosys {};
installPhase =
''
ODIR=fma_float_${toString data_width}_gsclib
mkdir -p $out/$ODIR/{log,nl}
cp out.log $out/$ODIR/log/top.log
cp nl.v $out/$ODIR/nl/top.nl.v
'';
buildInputs = [ pkgs.yosys sv2v ];
};
mk_fma_fixed_sky130 = {data_width, sum_width, clock_period} : pkgs.stdenv.mkDerivation {
name = "fma_fixed_${toString data_width}_${toString sum_width}_sky130";
src = ./.;
unpackPhase = "true";
buildPhase = run-librelane { verilog_file = "$src/fma_fixed.v"; inherit data_width; inherit sum_width; inherit clock_period;};
installPhase = ''
ODIR=fma_fixed_${toString data_width}_${toString sum_width}_sky130
mkdir -p $out/$ODIR
cp -r top/runs/run/final/. $out/$ODIR/
'';
buildInputs = [ librelane-pkg ];
};
mk_fma_float_sky130 = {data_width, clock_period}: pkgs.stdenv.mkDerivation {
name = "fma_float_${toString data_width}_sky130";
src = cvfpu-src;
srcExtra = ./.;
unpackPhase = "true";
buildPhase = run-sv2v {inherit data_width;} + run-librelane {inherit clock_period;};
installPhase =
''
ODIR=fma_float_${toString data_width}_sky130
mkdir -p $out/$ODIR
cp -r top/runs/run/final/. $out/$ODIR/
'';
buildInputs = [ librelane-pkg sv2v ];
};
in {
fma_fixed_8_24_gsclib = mk_fma_fixed_gsclib {data_width = 8; sum_width = 24; };
fma_fixed_16_40_gsclib = mk_fma_fixed_gsclib {data_width = 16; sum_width = 40; };
fma_fixed_32_72_gsclib = mk_fma_fixed_gsclib {data_width = 32; sum_width = 72; };
fma_fixed_8_24_sky130 = mk_fma_fixed_sky130 {data_width = 8; sum_width = 24; clock_period=20; };
fma_fixed_16_40_sky130 = mk_fma_fixed_sky130 {data_width = 16; sum_width = 40; clock_period=20; };
fma_fixed_32_72_sky130 = mk_fma_fixed_sky130 {data_width = 32; sum_width = 72; clock_period=20; };
fma_float_16_gsclib = mk_fma_float_gsclib {data_width = 16; };
fma_float_32_gsclib = mk_fma_float_gsclib {data_width = 32; };
fma_float_64_gsclib = mk_fma_float_gsclib {data_width = 64; };
fma_float_16_sky130 = mk_fma_float_sky130 {data_width = 16; clock_period=40; };
fma_float_32_sky130 = mk_fma_float_sky130 {data_width = 32; clock_period=50; };
fma_float_64_sky130 = mk_fma_float_sky130 {data_width = 64; clock_period=115; };
default = pkgs.symlinkJoin {
name = "fma_all";
paths = with self.packages.${system};
[
fma_fixed_8_24_gsclib
fma_fixed_16_40_gsclib
fma_fixed_32_72_gsclib
fma_fixed_8_24_sky130
fma_fixed_16_40_sky130
fma_fixed_32_72_sky130
fma_float_16_gsclib
fma_float_32_gsclib
fma_float_64_gsclib
fma_float_16_sky130
fma_float_32_sky130
fma_float_64_sky130
];
};
}
);
};
}
fma_fixed.v
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module top #(
parameter DATA_WIDTH = 32,
parameter SUM_WIDTH = 72
) (
input wire signed [DATA_WIDTH-1:0] i_weight,
input wire signed [DATA_WIDTH-1:0] i_activation,
input wire signed [SUM_WIDTH-1:0] i_sum,
output wire signed [SUM_WIDTH-1:0] o_sum
);
assign o_sum = (i_weight * i_activation) + i_sum;
endmodule
fma_float16.sv
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module top #(
parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::FP16,
parameter int unsigned NumPipeRegs = 0,
parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE,
parameter type TagType = logic,
parameter type AuxType = logic,
localparam int unsigned WIDTH = 16,
localparam int unsigned ExtRegEnaWidth = 1
) (
input logic clk_i,
input logic rst_ni,
// Input signals
input logic [2:0][WIDTH-1:0] operands_i, // 3 operands
input logic [2:0] is_boxed_i, // 3 operands
input fpnew_pkg::roundmode_e rnd_mode_i,
input fpnew_pkg::operation_e op_i,
input logic op_mod_i,
input TagType tag_i,
input logic mask_i,
input AuxType aux_i,
// Input Handshake
input logic in_valid_i,
output logic in_ready_o,
input logic flush_i,
// Output signals
output logic [WIDTH-1:0] result_o,
output fpnew_pkg::status_t status_o,
output logic extension_bit_o,
output TagType tag_o,
output logic mask_o,
output AuxType aux_o,
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
);
fpnew_fma #(
.FpFormat(FpFormat)
) top (
.clk_i(clk_i),
.rst_ni(rst_ni),
.operands_i(operands_i),
.is_boxed_i(is_boxed_i),
.rnd_mode_i(rnd_mode_i),
.op_i(op_i),
.op_mod_i(op_mod_i),
.tag_i(tag_i),
.mask_i(mask_i),
.aux_i(aux_i),
.in_valid_i(in_valid_i),
.in_ready_o(in_ready_o),
.flush_i(flush_i),
.result_o(result_o),
.status_o(status_o),
.extension_bit_o(extension_bit_o),
.tag_o(tag_o),
.mask_o(mask_o),
.aux_o(aux_o),
.out_valid_o(out_valid_o),
.out_ready_i(out_ready_i),
.busy_o(busy_o),
.reg_ena_i(reg_ena_i)
);
endmodule
fma_float32.sv
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module top #(
parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::FP32,
parameter int unsigned NumPipeRegs = 0,
parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE,
parameter type TagType = logic,
parameter type AuxType = logic,
localparam int unsigned WIDTH = 32,
localparam int unsigned ExtRegEnaWidth = 1
) (
input logic clk_i,
input logic rst_ni,
// Input signals
input logic [2:0][WIDTH-1:0] operands_i, // 3 operands
input logic [2:0] is_boxed_i, // 3 operands
input fpnew_pkg::roundmode_e rnd_mode_i,
input fpnew_pkg::operation_e op_i,
input logic op_mod_i,
input TagType tag_i,
input logic mask_i,
input AuxType aux_i,
// Input Handshake
input logic in_valid_i,
output logic in_ready_o,
input logic flush_i,
// Output signals
output logic [WIDTH-1:0] result_o,
output fpnew_pkg::status_t status_o,
output logic extension_bit_o,
output TagType tag_o,
output logic mask_o,
output AuxType aux_o,
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
);
fpnew_fma #(
.FpFormat(FpFormat)
) top (
.clk_i(clk_i),
.rst_ni(rst_ni),
.operands_i(operands_i),
.is_boxed_i(is_boxed_i),
.rnd_mode_i(rnd_mode_i),
.op_i(op_i),
.op_mod_i(op_mod_i),
.tag_i(tag_i),
.mask_i(mask_i),
.aux_i(aux_i),
.in_valid_i(in_valid_i),
.in_ready_o(in_ready_o),
.flush_i(flush_i),
.result_o(result_o),
.status_o(status_o),
.extension_bit_o(extension_bit_o),
.tag_o(tag_o),
.mask_o(mask_o),
.aux_o(aux_o),
.out_valid_o(out_valid_o),
.out_ready_i(out_ready_i),
.busy_o(busy_o),
.reg_ena_i(reg_ena_i)
);
endmodule
fma_float64.sv
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module top #(
parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::FP64,
parameter int unsigned NumPipeRegs = 0,
parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE,
parameter type TagType = logic,
parameter type AuxType = logic,
localparam int unsigned WIDTH = 64,
localparam int unsigned ExtRegEnaWidth = 1
) (
input logic clk_i,
input logic rst_ni,
// Input signals
input logic [2:0][WIDTH-1:0] operands_i, // 3 operands
input logic [2:0] is_boxed_i, // 3 operands
input fpnew_pkg::roundmode_e rnd_mode_i,
input fpnew_pkg::operation_e op_i,
input logic op_mod_i,
input TagType tag_i,
input logic mask_i,
input AuxType aux_i,
// Input Handshake
input logic in_valid_i,
output logic in_ready_o,
input logic flush_i,
// Output signals
output logic [WIDTH-1:0] result_o,
output fpnew_pkg::status_t status_o,
output logic extension_bit_o,
output TagType tag_o,
output logic mask_o,
output AuxType aux_o,
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o,
// External register enable override
input logic [ExtRegEnaWidth-1:0] reg_ena_i
);
fpnew_fma #(
.FpFormat(FpFormat)
) top (
.clk_i(clk_i),
.rst_ni(rst_ni),
.operands_i(operands_i),
.is_boxed_i(is_boxed_i),
.rnd_mode_i(rnd_mode_i),
.op_i(op_i),
.op_mod_i(op_mod_i),
.tag_i(tag_i),
.mask_i(mask_i),
.aux_i(aux_i),
.in_valid_i(in_valid_i),
.in_ready_o(in_ready_o),
.flush_i(flush_i),
.result_o(result_o),
.status_o(status_o),
.extension_bit_o(extension_bit_o),
.tag_o(tag_o),
.mask_o(mask_o),
.aux_o(aux_o),
.out_valid_o(out_valid_o),
.out_ready_i(out_ready_i),
.busy_o(busy_o),
.reg_ena_i(reg_ena_i)
);
endmodule
main.py
+6
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def main():
print("Hello from mlhw!")
if __name__ == "__main__":
main()
pyproject.toml
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[project]
name = "mlhw"
version = "0.1.0"
description = "Machine Learning Hardware Modules"
readme = "README.md"
requires-python = ">=3.14"
dependencies = []