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231 lines
7.1 KiB
231 lines
7.1 KiB
import numpy as np |
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from kyupy import sdf, verilog, bench |
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from kyupy.wave_sim import WaveSim, TMAX, TMIN |
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from kyupy.techlib import SAED32, SAED90 |
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def test_parse(): |
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test = ''' |
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(DELAYFILE |
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(SDFVERSION "OVI 2.1") |
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(DESIGN "test") |
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(DATE "Wed May 31 14:46:06 2017") |
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(VENDOR "saed90nm_max") |
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(PROGRAM "Synopsys Design Compiler cmos-annotated") |
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(VERSION "I-2013.12-ICC-SP3") |
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(DIVIDER /) |
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(VOLTAGE 1.20:1.20:1.20) |
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(PROCESS "TYPICAL") |
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(TEMPERATURE 25.00:25.00:25.00) |
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(TIMESCALE 1ns) |
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(CELL |
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(CELLTYPE "b14") |
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(INSTANCE) |
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(DELAY |
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(ABSOLUTE |
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(INTERCONNECT U621/ZN U19246/IN1 (0.000:0.000:0.000)) |
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(INTERCONNECT U13292/QN U19246/IN2 (0.001:0.001:0.001)) |
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(INTERCONNECT U15050/QN U19247/IN1 (0.000:0.000:0.000)) |
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(INTERCONNECT U13293/QN U19247/IN2 (0.000:0.000:0.000) (0.000:0.000:0.000)) |
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) |
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) |
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) |
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(CELL |
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(CELLTYPE "INVX2") |
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(INSTANCE U78) |
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(DELAY |
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(ABSOLUTE |
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(IOPATH INP ZN (0.201:0.227:0.227) (0.250:0.271:0.271)) |
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) |
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) |
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) |
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(CELL |
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(CELLTYPE "SDFFARX1") |
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(INSTANCE reg3_reg_1_0) |
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(DELAY |
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(ABSOLUTE |
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(IOPATH (posedge CLK) Q (0.707:0.710:0.710) (0.737:0.740:0.740)) |
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(IOPATH (negedge RSTB) Q () (0.909:0.948:0.948)) |
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(IOPATH (posedge CLK) QN (0.585:0.589:0.589) (0.545:0.550:0.550)) |
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(IOPATH (negedge RSTB) QN (1.546:1.593:1.593) ()) |
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) |
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) |
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(TIMINGCHECK |
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(WIDTH (posedge CLK) (0.284:0.284:0.284)) |
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(WIDTH (negedge CLK) (0.642:0.642:0.642)) |
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(SETUP (posedge D) (posedge CLK) (0.544:0.553:0.553)) |
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(SETUP (negedge D) (posedge CLK) (0.620:0.643:0.643)) |
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(HOLD (posedge D) (posedge CLK) (-0.321:-0.331:-0.331)) |
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(HOLD (negedge D) (posedge CLK) (-0.196:-0.219:-0.219)) |
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(RECOVERY (posedge RSTB) (posedge CLK) (-1.390:-1.455:-1.455)) |
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(HOLD (posedge RSTB) (posedge CLK) (1.448:1.509:1.509)) |
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(SETUP (posedge SE) (posedge CLK) (0.662:0.670:0.670)) |
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(SETUP (negedge SE) (posedge CLK) (0.698:0.702:0.702)) |
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(HOLD (posedge SE) (posedge CLK) (-0.435:-0.444:-0.444)) |
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(HOLD (negedge SE) (posedge CLK) (-0.291:-0.295:-0.295)) |
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(SETUP (posedge SI) (posedge CLK) (0.544:0.544:0.544)) |
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(SETUP (negedge SI) (posedge CLK) (0.634:0.688:0.688)) |
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(HOLD (posedge SI) (posedge CLK) (-0.317:-0.318:-0.318)) |
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(HOLD (negedge SI) (posedge CLK) (-0.198:-0.247:-0.247)) |
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(WIDTH (negedge RSTB) (0.345:0.345:0.345)) |
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))) |
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''' |
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df = sdf.parse(test) |
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assert df.name == 'test' |
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def test_b15(mydir): |
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df = sdf.load(mydir / 'b15_2ig.sdf.gz') |
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assert df.name == 'b15' |
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def test_gates(mydir): |
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c = verilog.load(mydir / 'gates.v', tlib=SAED90) |
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df = sdf.load(mydir / 'gates.sdf') |
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lt = df.iopaths(c, tlib=SAED90)[1] |
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nand_a = c.cells['nandgate'].ins[0] |
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nand_b = c.cells['nandgate'].ins[1] |
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and_a = c.cells['andgate'].ins[0] |
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and_b = c.cells['andgate'].ins[1] |
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assert lt[nand_a, 0, 0] == 0.103 |
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assert lt[nand_a, 0, 1] == 0.127 |
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assert lt[nand_b, 0, 0] == 0.086 |
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assert lt[nand_b, 0, 1] == 0.104 |
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assert lt[and_a, 0, 0] == 0.378 |
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assert lt[and_a, 0, 1] == 0.377 |
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assert lt[and_b, 0, 0] == 0.375 |
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assert lt[and_b, 0, 1] == 0.370 |
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def test_nand_xor(): |
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c = bench.parse(""" |
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input(A1,A2) |
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output(lt_1237_U91,lt_1237_U92) |
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lt_1237_U91 = NAND2X0_RVT(A1,A2) |
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lt_1237_U92 = XOR2X1_RVT(A1,A2) |
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""") |
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df = sdf.parse(""" |
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(DELAYFILE |
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(CELL |
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(CELLTYPE "NAND2X0_RVT") |
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(INSTANCE lt_1237_U91) |
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(DELAY |
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(ABSOLUTE |
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(IOPATH A1 Y (0.018:0.022:0.021) (0.017:0.019:0.019)) |
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(IOPATH A2 Y (0.021:0.024:0.024) (0.018:0.021:0.021)) |
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) |
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) |
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) |
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(CELL |
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(CELLTYPE "XOR2X1_RVT") |
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(INSTANCE lt_1237_U92) |
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(DELAY |
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(ABSOLUTE |
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(IOPATH (posedge A1) Y (0.035:0.038:0.038) (0.037:0.062:0.062)) |
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(IOPATH (negedge A1) Y (0.035:0.061:0.061) (0.036:0.040:0.040)) |
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(IOPATH (posedge A2) Y (0.042:0.043:0.043) (0.051:0.064:0.064)) |
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(IOPATH (negedge A2) Y (0.041:0.066:0.066) (0.051:0.053:0.053)) |
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) |
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) |
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) |
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) |
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""") |
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d = df.iopaths(c, tlib=SAED32)[1] |
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c.resolve_tlib_cells(SAED32) |
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sim = WaveSim(c, delays=d, sims=16) |
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# input A1 |
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sim.s[0,0] = [0,1,0,1] * 4 # initial values 0101010101010101 |
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sim.s[1,0] = 0.0 # transition time |
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sim.s[2,0] = [0,0,1,1] * 4 # final values 0011001100110011 |
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# input A2 |
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sim.s[0,1] = ([0]*4 + [1]*4)*2 # initial values 0000111100001111 |
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sim.s[1,1] = 0.0 # transition time |
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sim.s[2,1] = [0]*8 + [1]*8 # final values 0000000011111111 |
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# A1: 0FR10FR10FR10FR1 |
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# A2: 0000FFFFRRRR1111 |
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# nand: 11111RNR1NFF1RF0 |
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# xor: 0FR1FPPRRNPF1RF0 |
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sim.s_to_c() |
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sim.c_prop() |
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sim.c_to_s() |
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eat = sim.s[4,2:] |
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lst = sim.s[5,2:] |
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# NAND-gate output |
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assert np.allclose(eat[0], [ |
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TMAX, TMAX, TMAX, TMAX, TMAX, |
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0.022, # FF -> rising Y: min(0.022, 0.024) |
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TMAX, # RF: pulse filtered |
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0.024, # falling A2 -> rising Y |
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TMAX, |
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TMAX, # FR: pulse filtered |
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0.021, # RR -> falling Y: max(0.019, 0.021) |
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0.021, # rising A2 -> falling Y |
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TMAX, |
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0.022, # falling A1 -> rising Y |
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0.019, # rising A1 -> falling Y |
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TMAX |
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]) |
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assert np.allclose(lst[0], [ |
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TMIN, TMIN, TMIN, TMIN, TMIN, |
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0.022, # FF -> rising Y: min(0.022, 0.024) |
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TMIN, # RF: pulse filtered |
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0.024, # falling A2 -> rising Y |
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TMIN, |
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TMIN, # FR: pulse filtered |
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0.021, # RR -> falling Y: max(0.019, 0.021) |
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0.021, # rising A2 -> falling Y |
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TMIN, |
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0.022, # falling A1 -> rising Y |
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0.019, # rising A1 -> falling Y |
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TMIN |
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]) |
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#XOR-gate output |
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assert np.allclose(eat[1], [ |
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TMAX, |
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0.040, # A1:F -> Y:F |
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0.038, # A1:R -> Y:R |
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TMAX, |
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0.053, # A2:F -> Y:F |
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TMAX, # P filtered |
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TMAX, # P filtered |
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0.066, # A2:F -> Y:R |
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0.043, # A2:R -> Y:R |
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TMAX, # N filtered |
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TMAX, # P filtered |
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0.064, # A2:R -> Y:F |
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TMAX, |
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0.061, # A1:F -> Y:R |
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0.062, # A1:R -> Y:F |
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TMAX, |
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]) |
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assert np.allclose(lst[1], [ |
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TMIN, |
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0.040, # A1:F -> Y:F |
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0.038, # A1:R -> Y:R |
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TMIN, |
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0.053, # A2:F -> Y:F |
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TMIN, # P filtered |
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TMIN, # P filtered |
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0.066, # A2:F -> Y:R |
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0.043, # A2:R -> Y:R |
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TMIN, # N filtered |
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TMIN, # P filtered |
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0.064, # A2:R -> Y:F |
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TMIN, |
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0.061, # A1:F -> Y:R |
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0.062, # A1:R -> Y:F |
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TMIN, |
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]) |