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A python module for parsing, processing, and simulating gate-level circuits.
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kyupy/tests
Stefan Holst 44b0c887d7
random sampling of delays 		2 years ago
..
__init__.py Project Import 4 years ago
b01.bench Project Import 4 years ago
b01.v Project Import 4 years ago
b14.sdf.gz updated b14 benchmark, update wavesim capture api, expand usage examples 4 years ago
b14.stuck.stil.gz updated b14 benchmark, update wavesim capture api, expand usage examples 4 years ago
b14.transition.stil.gz updated b14 benchmark, update wavesim capture api, expand usage examples 4 years ago
b14.v.gz updated b14 benchmark, update wavesim capture api, expand usage examples 4 years ago
conftest.py random sampling of delays 2 years ago
gates.sdf Project Import 4 years ago
gates.v Project Import 4 years ago
test_bench.py interface -> io_nodes, io_loc fix 2 years ago
test_circuit.py interface -> io_nodes, io_loc fix 2 years ago
test_logic.py faster logic sim, removing MVArray, BPArray 2 years ago
test_logic_sim.py faster logic sim, removing MVArray, BPArray 2 years ago
test_sdf.py TechLib class, remove unnecessary .index 4 years ago
test_stil.py faster logic sim, removing MVArray, BPArray 2 years ago
test_verilog.py Documentation, cleanup, multi-valued logic 4 years ago
test_wave_sim.py random sampling of delays 2 years ago