A python module for parsing, processing, and simulating gate-level circuits.
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from kyupy import verilog |
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def test_b01(mydir): |
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with open(mydir / 'b01.v', 'r') as f: |
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modules = verilog.parse(f.read()) |
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assert modules is not None |
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assert verilog.parse(mydir / 'b01.v') is not None |
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