A python module for parsing, processing, and simulating gate-level circuits.

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kyupy/kyupy

History

Stefan Holst e6ae009969 updated b14 benchmark, update wavesim capture api, expand usage examples		4 years ago
..
__init__.py	support more SAED cells, improve verilog parsing, fix inspection warnings	4 years ago
bench.py	Project Import	4 years ago
bittools.py	Project Import	4 years ago
circuit.py	Project Import	4 years ago
logic_sim.py	fix loading of stuck-at fault patterns, support ibuff cell	4 years ago
packed_vectors.py	Project Import	4 years ago
saed.py	support more SAED cells, improve verilog parsing, fix inspection warnings	4 years ago
sdf.py	support more SAED cells, improve verilog parsing, fix inspection warnings	4 years ago
stil.py	updated b14 benchmark, update wavesim capture api, expand usage examples	4 years ago
verilog.py	support more SAED cells, improve verilog parsing, fix inspection warnings	4 years ago
wave_sim.py	updated b14 benchmark, update wavesim capture api, expand usage examples	4 years ago
wave_sim_cuda.py	updated b14 benchmark, update wavesim capture api, expand usage examples	4 years ago