A python module for parsing, processing, and simulating gate-level circuits.
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Stefan Holst
e6ae009969
updated b14 benchmark, update wavesim capture api, expand usage examples
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5 years ago |
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__init__.py
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support more SAED cells, improve verilog parsing, fix inspection warnings
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5 years ago |
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bench.py
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Project Import
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5 years ago |
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bittools.py
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Project Import
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5 years ago |
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circuit.py
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Project Import
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5 years ago |
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logic_sim.py
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fix loading of stuck-at fault patterns, support ibuff cell
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5 years ago |
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packed_vectors.py
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Project Import
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5 years ago |
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saed.py
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support more SAED cells, improve verilog parsing, fix inspection warnings
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5 years ago |
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sdf.py
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support more SAED cells, improve verilog parsing, fix inspection warnings
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5 years ago |
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stil.py
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updated b14 benchmark, update wavesim capture api, expand usage examples
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5 years ago |
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verilog.py
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support more SAED cells, improve verilog parsing, fix inspection warnings
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5 years ago |
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wave_sim.py
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updated b14 benchmark, update wavesim capture api, expand usage examples
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5 years ago |
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wave_sim_cuda.py
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updated b14 benchmark, update wavesim capture api, expand usage examples
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5 years ago |