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100 lines
3.3 KiB
100 lines
3.3 KiB
from kyupy import sdf, verilog |
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from kyupy.saed import pin_index |
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def test_parse(): |
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test = ''' |
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(DELAYFILE |
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(SDFVERSION "OVI 2.1") |
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(DESIGN "test") |
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(DATE "Wed May 31 14:46:06 2017") |
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(VENDOR "saed90nm_max") |
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(PROGRAM "Synopsys Design Compiler cmos-annotated") |
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(VERSION "I-2013.12-ICC-SP3") |
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(DIVIDER /) |
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(VOLTAGE 1.20:1.20:1.20) |
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(PROCESS "TYPICAL") |
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(TEMPERATURE 25.00:25.00:25.00) |
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(TIMESCALE 1ns) |
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(CELL |
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(CELLTYPE "b14") |
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(INSTANCE) |
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(DELAY |
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(ABSOLUTE |
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(INTERCONNECT U621/ZN U19246/IN1 (0.000:0.000:0.000)) |
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(INTERCONNECT U13292/QN U19246/IN2 (0.001:0.001:0.001)) |
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(INTERCONNECT U15050/QN U19247/IN1 (0.000:0.000:0.000)) |
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(INTERCONNECT U13293/QN U19247/IN2 (0.000:0.000:0.000) (0.000:0.000:0.000)) |
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) |
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) |
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) |
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(CELL |
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(CELLTYPE "INVX2") |
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(INSTANCE U78) |
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(DELAY |
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(ABSOLUTE |
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(IOPATH INP ZN (0.201:0.227:0.227) (0.250:0.271:0.271)) |
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) |
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) |
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) |
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(CELL |
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(CELLTYPE "SDFFARX1") |
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(INSTANCE reg3_reg_1_0) |
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(DELAY |
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(ABSOLUTE |
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(IOPATH (posedge CLK) Q (0.707:0.710:0.710) (0.737:0.740:0.740)) |
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(IOPATH (negedge RSTB) Q () (0.909:0.948:0.948)) |
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(IOPATH (posedge CLK) QN (0.585:0.589:0.589) (0.545:0.550:0.550)) |
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(IOPATH (negedge RSTB) QN (1.546:1.593:1.593) ()) |
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) |
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) |
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(TIMINGCHECK |
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(WIDTH (posedge CLK) (0.284:0.284:0.284)) |
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(WIDTH (negedge CLK) (0.642:0.642:0.642)) |
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(SETUP (posedge D) (posedge CLK) (0.544:0.553:0.553)) |
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(SETUP (negedge D) (posedge CLK) (0.620:0.643:0.643)) |
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(HOLD (posedge D) (posedge CLK) (-0.321:-0.331:-0.331)) |
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(HOLD (negedge D) (posedge CLK) (-0.196:-0.219:-0.219)) |
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(RECOVERY (posedge RSTB) (posedge CLK) (-1.390:-1.455:-1.455)) |
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(HOLD (posedge RSTB) (posedge CLK) (1.448:1.509:1.509)) |
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(SETUP (posedge SE) (posedge CLK) (0.662:0.670:0.670)) |
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(SETUP (negedge SE) (posedge CLK) (0.698:0.702:0.702)) |
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(HOLD (posedge SE) (posedge CLK) (-0.435:-0.444:-0.444)) |
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(HOLD (negedge SE) (posedge CLK) (-0.291:-0.295:-0.295)) |
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(SETUP (posedge SI) (posedge CLK) (0.544:0.544:0.544)) |
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(SETUP (negedge SI) (posedge CLK) (0.634:0.688:0.688)) |
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(HOLD (posedge SI) (posedge CLK) (-0.317:-0.318:-0.318)) |
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(HOLD (negedge SI) (posedge CLK) (-0.198:-0.247:-0.247)) |
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(WIDTH (negedge RSTB) (0.345:0.345:0.345)) |
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))) |
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''' |
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df = sdf.parse(test) |
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assert df.name == 'test' |
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# print(f'DelayFile(name={df.name}, interconnects={len(df.interconnects)}, iopaths={len(df.iopaths)})') |
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def test_b14(mydir): |
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df = sdf.parse(mydir / 'b14.sdf.gz') |
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assert df.name == 'b14' |
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def test_gates(mydir): |
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c = verilog.parse(mydir / 'gates.v') |
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df = sdf.parse(mydir / 'gates.sdf') |
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lt = df.annotation(c, pin_index, dataset=1) |
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nand_a = c.cells['nandgate'].ins[0] |
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nand_b = c.cells['nandgate'].ins[1] |
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and_a = c.cells['andgate'].ins[0] |
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and_b = c.cells['andgate'].ins[1] |
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assert lt[nand_a.index, 0, 0] == 0.103 |
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assert lt[nand_a.index, 0, 1] == 0.127 |
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assert lt[nand_b.index, 0, 0] == 0.086 |
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assert lt[nand_b.index, 0, 1] == 0.104 |
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assert lt[and_a.index, 0, 0] == 0.378 |
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assert lt[and_a.index, 0, 1] == 0.377 |
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assert lt[and_b.index, 0, 0] == 0.375 |
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assert lt[and_b.index, 0, 1] == 0.370
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