A python module for parsing, processing, and simulating gate-level circuits.

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Tree: df695e0aa1

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v0.0.1

v0.0.2

v0.0.3

v0.0.4

v0.0.5

v0.0.6

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kyupy/docs

History

Stefan Holst df695e0aa1 for release 0.0.6 ... - sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API) - sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic - Circuit: dot output fix and better style, fixed equivalence check of lines and nodes. - Techlib: Added KYUPY library with supported simulation primitives for debug and testing - tests: fixed and added more for better coverage - more type annotations - updated project config and dependencies for better uv experience, newer lark, newer numpy		3 weeks ago
..
Makefile	migrate readme to markdown	3 weeks ago
circuit.rst	for release 0.0.4	2 years ago
conf.py	migrate readme to markdown	3 weeks ago
index.rst	migrate readme to markdown	3 weeks ago
logic.rst	for release 0.0.4	2 years ago
miscellaneous.rst	for release 0.0.4	2 years ago
parsers.rst	for release 0.0.4	2 years ago
simulators.rst	for release 0.0.6	3 weeks ago
techlib.rst	for release 0.0.4	2 years ago