A python module for parsing, processing, and simulating gate-level circuits.

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kyupy/src/kyupy

History

Stefan Holst c49667edc1 remove old code, verilog positional pins		2 years ago
..
__init__.py	docs	2 years ago
bench.py	doc improvements	2 years ago
circuit.py	circuit node substitution	2 years ago
logic.py	support more cells in logic sim	2 years ago
logic_sim.py	sim support for remaining primitives	2 years ago
sdf.py	doc improvements	2 years ago
sim.py	sim support for remaining primitives	2 years ago
stil.py	doc improvements	2 years ago
techlib.py	remove old code, verilog positional pins	2 years ago
verilog.py	remove old code, verilog positional pins	2 years ago
wave_sim.py	docs	2 years ago