A python module for parsing, processing, and simulating gate-level circuits.
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Stefan Holst c49667edc1 remove old code, verilog positional pins 1 year ago
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__init__.py docs 1 year ago
bench.py doc improvements 1 year ago
circuit.py circuit node substitution 1 year ago
logic.py support more cells in logic sim 1 year ago
logic_sim.py sim support for remaining primitives 1 year ago
sdf.py doc improvements 1 year ago
sim.py sim support for remaining primitives 1 year ago
stil.py doc improvements 1 year ago
techlib.py remove old code, verilog positional pins 1 year ago
verilog.py remove old code, verilog positional pins 1 year ago
wave_sim.py docs 1 year ago