A python module for parsing, processing, and simulating gate-level circuits.
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Stefan Holst
64e1de396f
New m-valued logic arrays, documentation, 0.0.2
- MVArray for multi-valued logic
- BPArray for bit-parallel storage layout
- Started documenting with Sphinx
- Migrated simulators to new BPArray
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4 years ago |
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__init__.py
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Project Import
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4 years ago |
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b01.bench
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Project Import
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4 years ago |
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b01.v
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Project Import
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4 years ago |
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b14.sdf.gz
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updated b14 benchmark, update wavesim capture api, expand usage examples
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4 years ago |
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b14.stuck.stil.gz
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updated b14 benchmark, update wavesim capture api, expand usage examples
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4 years ago |
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b14.transition.stil.gz
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updated b14 benchmark, update wavesim capture api, expand usage examples
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4 years ago |
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b14.v.gz
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updated b14 benchmark, update wavesim capture api, expand usage examples
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4 years ago |
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conftest.py
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Project Import
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4 years ago |
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gates.sdf
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Project Import
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4 years ago |
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gates.v
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Project Import
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4 years ago |
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test_bench.py
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New m-valued logic arrays, documentation, 0.0.2
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4 years ago |
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test_circuit.py
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New m-valued logic arrays, documentation, 0.0.2
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4 years ago |
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test_logic.py
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New m-valued logic arrays, documentation, 0.0.2
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4 years ago |
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test_logic_sim.py
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New m-valued logic arrays, documentation, 0.0.2
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4 years ago |
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test_sdf.py
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New m-valued logic arrays, documentation, 0.0.2
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4 years ago |
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test_stil.py
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New m-valued logic arrays, documentation, 0.0.2
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4 years ago |
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test_verilog.py
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New m-valued logic arrays, documentation, 0.0.2
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4 years ago |
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test_wave_sim.py
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New m-valued logic arrays, documentation, 0.0.2
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4 years ago |
