A python module for parsing, processing, and simulating gate-level circuits.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
Stefan Holst 35e727e714 better docs, new techlib as default, fix tests 1 year ago
..
Makefile docs, fix stil unassigned, fix io_locs for busses 1 year ago
circuit.rst docs 1 year ago
conf.py cleanup and new intro notebook 2 years ago
index.rst better docs, new techlib as default, fix tests 1 year ago
logic.rst docs 1 year ago
miscellaneous.rst better docs, new techlib as default, fix tests 1 year ago
parsers.rst Documentation, cleanup, multi-valued logic 4 years ago
simulators.rst better docs, new techlib as default, fix tests 1 year ago
techlib.rst better docs, new techlib as default, fix tests 1 year ago