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298 lines
9.7 KiB
298 lines
9.7 KiB
import numpy as np |
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from kyupy.logic_sim import LogicSim, LogicSim6V |
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from kyupy import bench, logic, sim |
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from kyupy.logic import mvarray, bparray, bp_to_mv, mv_to_bp |
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def assert_equal_shape_and_contents(actual, desired): |
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desired = np.array(desired, dtype=np.uint8) |
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assert actual.shape == desired.shape |
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np.testing.assert_allclose(actual, desired) |
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def test_2v(): |
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c = bench.parse(f''' |
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input(i3, i2, i1, i0) |
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output({",".join([f"o{i:02d}" for i in range(33)])}) |
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o00=BUF1(i0) |
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o01=INV1(i0) |
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o02=AND2(i0,i1) |
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o03=AND3(i0,i1,i2) |
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o04=AND4(i0,i1,i2,i3) |
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o05=NAND2(i0,i1) |
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o06=NAND3(i0,i1,i2) |
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o07=NAND4(i0,i1,i2,i3) |
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o08=OR2(i0,i1) |
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o09=OR3(i0,i1,i2) |
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o10=OR4(i0,i1,i2,i3) |
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o11=NOR2(i0,i1) |
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o12=NOR3(i0,i1,i2) |
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o13=NOR4(i0,i1,i2,i3) |
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o14=XOR2(i0,i1) |
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o15=XOR3(i0,i1,i2) |
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o16=XOR4(i0,i1,i2,i3) |
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o17=XNOR2(i0,i1) |
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o18=XNOR3(i0,i1,i2) |
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o19=XNOR4(i0,i1,i2,i3) |
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o20=AO21(i0,i1,i2) |
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o21=OA21(i0,i1,i2) |
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o22=AO22(i0,i1,i2,i3) |
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o23=OA22(i0,i1,i2,i3) |
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o24=AOI21(i0,i1,i2) |
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o25=OAI21(i0,i1,i2) |
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o26=AOI22(i0,i1,i2,i3) |
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o27=OAI22(i0,i1,i2,i3) |
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o28=AO211(i0,i1,i2,i3) |
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o29=OA211(i0,i1,i2,i3) |
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o30=AOI211(i0,i1,i2,i3) |
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o31=OAI211(i0,i1,i2,i3) |
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o32=MUX21(i0,i1,i2) |
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''') |
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s = LogicSim(c, 16, m=2) |
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bpa = logic.bparray([f'{i:04b}'+('-'*(s.s_len-4)) for i in range(16)]) |
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s.s[0] = bpa |
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s.s_to_c() |
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s.c_prop() |
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s.c_to_s() |
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mva = logic.bp_to_mv(s.s[1]) |
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for res, exp in zip(logic.packbits(mva[4:], dtype=np.uint32), [ |
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sim.BUF1, sim.INV1, |
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sim.AND2, sim.AND3, sim.AND4, |
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sim.NAND2, sim.NAND3, sim.NAND4, |
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sim.OR2, sim.OR3, sim.OR4, |
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sim.NOR2, sim.NOR3, sim.NOR4, |
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sim.XOR2, sim.XOR3, sim.XOR4, |
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sim.XNOR2, sim.XNOR3, sim.XNOR4, |
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sim.AO21, sim.OA21, |
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sim.AO22, sim.OA22, |
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sim.AOI21, sim.OAI21, |
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sim.AOI22, sim.OAI22, |
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sim.AO211, sim.OA211, |
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sim.AOI211, sim.OAI211, |
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sim.MUX21 |
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]): |
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assert res == exp, f'Mismatch for SimPrim {sim.names[exp]} res={bin(res)} exp={bin(exp)}' |
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def test_4v(): |
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c = bench.parse('input(x, y) output(a, o, n) a=and(x,y) o=or(x,y) n=not(x)') |
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s = LogicSim(c, 16, m=4) |
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assert s.s_len == 5 |
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bpa = bparray( |
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'00---', '01---', '0----', '0X---', |
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'10---', '11---', '1----', '1X---', |
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'-0---', '-1---', '-----', '-X---', |
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'X0---', 'X1---', 'X----', 'XX---') |
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s.s[0] = bpa |
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s.s_to_c() |
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s.c_prop() |
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s.c_to_s() |
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mva = bp_to_mv(s.s[1]) |
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assert_equal_shape_and_contents(mva, mvarray( |
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'--001', '--011', '--0X1', '--0X1', |
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'--010', '--110', '--X10', '--X10', |
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'--0XX', '--X1X', '--XXX', '--XXX', |
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'--0XX', '--X1X', '--XXX', '--XXX')) |
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def test_4v_fault(): |
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c = bench.parse('input(x, y) output(a) a=and(x,y)') |
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s = LogicSim(c, 16, m=4) |
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assert s.s_len == 3 |
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bpa = bparray( |
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'00-', '01-', '0--', '0X-', |
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'10-', '11-', '1--', '1X-', |
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'-0-', '-1-', '---', '-X-', |
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'X0-', 'X1-', 'X--', 'XX-') |
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s.s[0] = bpa |
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s.s_to_c() |
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s.c_prop() |
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s.c_to_s() |
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mva = bp_to_mv(s.s[1]) |
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assert_equal_shape_and_contents(mva, mvarray( |
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'--0', '--0', '--0', '--0', |
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'--0', '--1', '--X', '--X', |
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'--0', '--X', '--X', '--X', |
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'--0', '--X', '--X', '--X')) |
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fault_line = s.circuit.cells['a'].ins[0] |
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s.s_to_c() |
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s.c_prop(fault_line=fault_line, fault_model=1) |
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s.c_to_s() |
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mva = bp_to_mv(s.s[1]) |
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assert_equal_shape_and_contents(mva, mvarray( |
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'--0', '--1', '--X', '--X', |
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'--0', '--1', '--X', '--X', |
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'--0', '--1', '--X', '--X', |
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'--0', '--1', '--X', '--X')) |
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s.s_to_c() |
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s.c_prop(fault_line=fault_line, fault_model=0) |
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s.c_to_s() |
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mva = bp_to_mv(s.s[1]) |
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assert_equal_shape_and_contents(mva, mvarray( |
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'--0', '--0', '--0', '--0', |
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'--0', '--0', '--0', '--0', |
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'--0', '--0', '--0', '--0', |
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'--0', '--0', '--0', '--0')) |
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def test_6v(): |
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c = bench.parse('input(x, y) output(a, o, n, xo, no) a=AND2(x,y) o=OR2(x,y) n=INV1(x) xo=XOR2(x,y) no=NOR2(x,y)') |
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s = LogicSim6V(c, 36) |
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assert s.s_len == 7 |
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mva = mvarray( |
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'0000101', '0101110', '0R0R1RF', '0F0F1FR', '0P0P1PN', '0N0N1NP', |
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'1001010', '1111000', '1RR10F0', '1FF10R0', '1PP10N0', '1NN10P0', |
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'R00RFRF', 'R1R1FF0', 'RRRRFPF', 'RFPNFNP', 'RPPRFRF', 'RNRNFFP', |
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'F00FRFR', 'F1F1RR0', 'FRPNRNP', 'FFFFRPR', 'FPPFRFR', 'FNFNRRP', |
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'P00PNPN', 'P1P1NN0', 'PRPRNRF', 'PFPFNFR', 'PPPPNPN', 'PNPNNNP', |
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'N00NPNP', 'N1N1PP0', 'NRRNPFP', 'NFFNPRP', 'NPPNPNP', 'NNNNPPP') |
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tests = np.copy(mva) |
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tests[2:] = logic.ZERO |
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s.s[0] = tests |
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s.s_to_c() |
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s.c_prop() |
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s.c_to_s() |
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resp = s.s[1].copy() |
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exp_resp = np.copy(mva) |
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exp_resp[:2] = logic.ZERO |
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np.testing.assert_allclose(resp, exp_resp) |
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def test_8v(): |
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c = bench.parse('input(x, y) output(a, o, n, xo) a=and(x,y) o=or(x,y) n=not(x) xo=xor(x,y)') |
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s = LogicSim(c, 64, m=8) |
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assert s.s_len == 6 |
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mva = mvarray( |
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'000010', '010111', '0-0X1X', '0X0X1X', '0R0R1R', '0F0F1F', '0P0P1P', '0N0N1N', |
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'100101', '111100', '1-X10X', '1XX10X', '1RR10F', '1FF10R', '1PP10N', '1NN10P', |
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'-00XXX', '-1X1XX', '--XXXX', '-XXXXX', '-RXXXX', '-FXXXX', '-PXXXX', '-NXXXX', |
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'X00XXX', 'X1X1XX', 'X-XXXX', 'XXXXXX', 'XRXXXX', 'XFXXXX', 'XPXXXX', 'XNXXXX', |
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'R00RFR', 'R1R1FF', 'R-XXFX', 'RXXXFX', 'RRRRFP', 'RFPNFN', 'RPPRFR', 'RNRNFF', |
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'F00FRF', 'F1F1RR', 'F-XXRX', 'FXXXRX', 'FRPNRN', 'FFFFRP', 'FPPFRF', 'FNFNRR', |
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'P00PNP', 'P1P1NN', 'P-XXNX', 'PXXXNX', 'PRPRNR', 'PFPFNF', 'PPPPNP', 'PNPNNN', |
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'N00NPN', 'N1N1PP', 'N-XXPX', 'NXXXPX', 'NRRNPF', 'NFFNPR', 'NPPNPN', 'NNNNPP') |
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tests = np.copy(mva) |
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tests[2:] = logic.UNASSIGNED |
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bpa = mv_to_bp(tests) |
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s.s[0] = bpa |
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s.s_to_c() |
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s.c_prop() |
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s.c_to_s() |
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resp = bp_to_mv(s.s[1]) |
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exp_resp = np.copy(mva) |
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exp_resp[:2] = logic.UNASSIGNED |
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np.testing.assert_allclose(resp, exp_resp) |
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def test_loop(): |
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c = bench.parse('q=dff(d) d=not(q)') |
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s = LogicSim(c, 4, m=8) |
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assert s.s_len == 1 |
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mva = mvarray([['0'], ['1'], ['R'], ['F']]) |
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# TODO |
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# s.assign(BPArray(mva)) |
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# s.propagate() |
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# resp_bp = BPArray((len(s.interface), s.sims)) |
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# s.capture(resp_bp) |
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# resp = MVArray(resp_bp) |
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# assert resp[0] == '1' |
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# assert resp[1] == '0' |
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# assert resp[2] == 'F' |
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# assert resp[3] == 'R' |
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# resp_bp = s.cycle(resp_bp) |
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# resp = MVArray(resp_bp) |
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# assert resp[0] == '0' |
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# assert resp[1] == '1' |
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# assert resp[2] == 'R' |
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# assert resp[3] == 'F' |
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def test_latch(): |
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c = bench.parse('input(d, t) output(q) q=latch(d, t)') |
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s = LogicSim(c, 8, m=8) |
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assert s.s_len == 4 |
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mva = mvarray('00-0', '00-1', '01-0', '01-1', '10-0', '10-1', '11-0', '11-1') |
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exp = mvarray('0000', '0011', '0100', '0100', '1000', '1011', '1111', '1111') |
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# TODO |
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# resp = MVArray(s.cycle(BPArray(mva))) |
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# for i in range(len(mva)): |
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# assert resp[i] == exp[i] |
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def test_b01(mydir): |
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c = bench.load(mydir / 'b01.bench') |
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# 8-valued |
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s = LogicSim(c, 8, m=8) |
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mva = np.zeros((s.s_len, 8), dtype=np.uint8) |
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s.s[0] = mv_to_bp(mva) |
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s.s_to_c() |
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s.c_prop() |
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s.c_to_s() |
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bp_to_mv(s.s[1]) |
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def sim_and_compare(c, test_resp, m=8): |
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tests, resp = test_resp |
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lsim = LogicSim(c, m=m, sims=tests.shape[1]) |
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lsim.s[0] = logic.mv_to_bp(tests) |
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lsim.s_to_c() |
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lsim.c_prop() |
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lsim.c_to_s() |
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resp_sim = logic.bp_to_mv(lsim.s[1])[:,:tests.shape[1]] |
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idxs, pats = np.nonzero(((resp == logic.ONE) & (resp_sim != logic.ONE)) | ((resp == logic.ZERO) & (resp_sim != logic.ZERO))) |
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for i, (idx, pat) in enumerate(zip(idxs, pats)): |
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if i >= 10: |
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print(f'...') |
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break |
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print(f'mismatch pattern:{pat} ppio:{idx} exp:{logic.mv_str(resp[idx,pat])} act:{logic.mv_str(resp_sim[idx,pat])}') |
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assert len(idxs) == 0 |
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def sim_and_compare_6v(c, test_resp): |
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tests, resp = test_resp |
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lsim = LogicSim6V(c, sims=tests.shape[1]) |
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lsim.s[0] = tests |
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lsim.s_to_c() |
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lsim.c_prop() |
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lsim.c_to_s() |
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resp_sim = lsim.s[1] |
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idxs, pats = np.nonzero(((resp == logic.ONE) & (resp_sim != logic.ONE)) | ((resp == logic.ZERO) & (resp_sim != logic.ZERO))) |
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for i, (idx, pat) in enumerate(zip(idxs, pats)): |
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if i >= 10: |
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print(f'...') |
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break |
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print(f'mismatch pattern:{pat} ppio:{idx} exp:{logic.mv_str(resp[idx,pat])} act:{logic.mv_str(resp_sim[idx,pat])}') |
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assert len(idxs) == 0 |
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def test_b15_2ig_sa_2v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp): |
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sim_and_compare(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp, m=2) |
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def test_b15_2ig_sa_4v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp): |
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sim_and_compare(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp, m=4) |
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def test_b15_2ig_sa_6v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp): |
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sim_and_compare_6v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp) |
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def test_b15_2ig_sa_8v(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp): |
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sim_and_compare(b15_2ig_circuit_resolved, b15_2ig_sa_nf_test_resp, m=8) |
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def test_b15_4ig_sa_2v(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp): |
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sim_and_compare(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp, m=2) |
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def test_b15_4ig_sa_4v(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp): |
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sim_and_compare(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp, m=4) |
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def test_b15_4ig_sa_8v(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp): |
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sim_and_compare(b15_4ig_circuit_resolved, b15_4ig_sa_rf_test_resp, m=8)
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