Stefan Holst afb0a64953 wsa accumulation in wavesim

2023-07-03 00:48:58 +09:00

..

__init__.py

Project Import

2020-10-29 16:45:33 +09:00

b01.bench

Project Import

2020-10-29 16:45:33 +09:00

b01.v

Project Import

2020-10-29 16:45:33 +09:00

b14.sdf.gz

updated b14 benchmark, update wavesim capture api, expand usage examples

2020-11-29 22:32:47 +09:00

b14.stuck.stil.gz

updated b14 benchmark, update wavesim capture api, expand usage examples

2020-11-29 22:32:47 +09:00

b14.transition.stil.gz

updated b14 benchmark, update wavesim capture api, expand usage examples

2020-11-29 22:32:47 +09:00

b14.v.gz

updated b14 benchmark, update wavesim capture api, expand usage examples

2020-11-29 22:32:47 +09:00

b15_2ig.sa_nf.stil.gz

new into demo

2023-06-19 14:01:31 +09:00

b15_2ig.sdf.gz

new into demo

2023-06-19 14:01:31 +09:00

b15_2ig.tf_nf.stil.gz

new into demo

2023-06-19 14:01:31 +09:00

b15_2ig.v.gz

doc improvements

2023-06-19 17:05:39 +09:00

b15_4ig.sdf.gz

doc improvements

2023-06-19 17:05:39 +09:00

b15_4ig.v.gz

doc improvements

2023-06-19 17:05:39 +09:00

conftest.py

random sampling of delays

2023-03-19 20:30:27 +09:00

gates.sdf

Project Import

2020-10-29 16:45:33 +09:00

gates.v

Project Import

2020-10-29 16:45:33 +09:00

test_bench.py

interface -> io_nodes, io_loc fix

2023-02-24 21:56:29 +09:00

test_circuit.py

circuit node substitution

2023-06-25 22:26:52 +09:00

test_logic_sim.py

faster logic sim, removing MVArray, BPArray

2023-03-12 23:59:10 +09:00

test_logic.py

support more cells in logic sim

2023-06-24 13:34:35 +09:00

test_sdf.py

doc improvements

2023-06-19 17:05:39 +09:00

test_stil.py

faster logic sim, removing MVArray, BPArray

2023-03-12 23:59:10 +09:00

test_verilog.py

support concat, bus select, ISOL cells

2023-06-24 23:41:08 +09:00

test_wave_sim.py

wsa accumulation in wavesim

2023-07-03 00:48:58 +09:00