stefan dd4e5c861a fix sim model generation for circuits with dangling nodes

2025-11-20 15:28:41 +09:00

..

__init__.py

Project Import

2020-10-29 16:45:33 +09:00

all_kyupy_simprims.minimal.v

4v sim, fixed 6v sim, better testing

2025-11-09 08:09:46 +09:00

all_kyupy_simprims.v

4v sim, fixed 6v sim, better testing

2025-11-09 08:09:46 +09:00

b01.bench

Project Import

2020-10-29 16:45:33 +09:00

b01.v

Project Import

2020-10-29 16:45:33 +09:00

b15_2ig.sa_nf.stil.gz

new into demo

2023-06-19 14:01:31 +09:00

b15_2ig.sdf.gz

new into demo

2023-06-19 14:01:31 +09:00

b15_2ig.tf_nf.stil.gz

new into demo

2023-06-19 14:01:31 +09:00

b15_2ig.v.gz

doc improvements

2023-06-19 17:05:39 +09:00

b15_4ig.sa_rf.stil.gz

alap toposort, improve tests

2023-11-07 12:44:19 +09:00

b15_4ig.sdf.gz

doc improvements

2023-06-19 17:05:39 +09:00

b15_4ig.v.gz

doc improvements

2023-06-19 17:05:39 +09:00

conftest.py

mux21 in 6v logic sim, more test fixtures

2024-04-06 15:22:46 +09:00

gates.sdf

cond in sdf parser. ignored for now.

2023-09-11 23:44:28 +09:00

gates.v

cond in sdf parser. ignored for now.

2023-09-11 23:44:28 +09:00

kyupy_simprims.genlib

new logic sim interface prototype, simprim lib and test

2025-11-02 20:56:14 +09:00

Makefile

4v sim, fixed 6v sim, better testing

2025-11-09 08:09:46 +09:00

map_to_minimal.abc

new logic sim interface prototype, simprim lib and test

2025-11-02 20:56:14 +09:00

minimal.genlib

new logic sim interface prototype, simprim lib and test

2025-11-02 20:56:14 +09:00

rng_haltonBase2.synth_yosys.v

better docs, new techlib as default, fix tests

2023-07-22 13:11:11 +09:00

test_bench.py

interface -> io_nodes, io_loc fix

2023-02-24 21:56:29 +09:00

test_circuit.py

euivalence test, op format doc

2025-10-31 17:13:58 +09:00

test_logic_sim.py

fix sim model generation for circuits with dangling nodes

2025-11-20 15:28:41 +09:00

test_logic.py

support more cells in logic sim

2023-06-24 13:34:35 +09:00

test_sdf.py

cond in sdf parser. ignored for now.

2023-09-11 23:44:28 +09:00

test_stil.py

better docs, new techlib as default, fix tests

2023-07-22 13:11:11 +09:00

test_verilog.py

cond in sdf parser. ignored for now.

2023-09-11 23:44:28 +09:00

test_wave_sim.py

fault injection for 4v sim, wave_sim test fix

2025-10-23 21:26:52 +09:00