A python module for parsing, processing, and simulating gate-level circuits.

You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Tree: 0c5a7f56e1

devel

main

v0.0.1

v0.0.2

v0.0.3

v0.0.4

v0.0.5

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from '0c5a7f56e1'

${ noResults }

kyupy/tests

History

Stefan Holst 0c5a7f56e1 Project Import		5 years ago
..
__init__.py	Project Import	5 years ago
b01.bench	Project Import	5 years ago
b01.v	Project Import	5 years ago
b14.sdf.gz	Project Import	5 years ago
b14.stil.gz	Project Import	5 years ago
b14.v.gz	Project Import	5 years ago
conftest.py	Project Import	5 years ago
gates.sdf	Project Import	5 years ago
gates.v	Project Import	5 years ago
test_bench.py	Project Import	5 years ago
test_circuit.py	Project Import	5 years ago
test_logic_sim.py	Project Import	5 years ago
test_packed_vectors.py	Project Import	5 years ago
test_sdf.py	Project Import	5 years ago
test_stil.py	Project Import	5 years ago
test_verilog.py	Project Import	5 years ago
test_wave_sim.py	Project Import	5 years ago