A python module for parsing, processing, and simulating gate-level circuits.

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v0.0.1

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v0.0.4

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kyupy/tests

History

Stefan Holst 351d809306 for release 0.0.4 ... - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements		1 year ago
..
__init__.py	Project Import	4 years ago
b01.bench	Project Import	4 years ago
b01.v	Project Import	4 years ago
b15_2ig.sa_nf.stil.gz	for release 0.0.4	1 year ago
b15_2ig.sdf.gz	for release 0.0.4	1 year ago
b15_2ig.tf_nf.stil.gz	for release 0.0.4	1 year ago
b15_2ig.v.gz	for release 0.0.4	1 year ago
b15_4ig.sdf.gz	for release 0.0.4	1 year ago
b15_4ig.v.gz	for release 0.0.4	1 year ago
conftest.py	for release 0.0.4	1 year ago
gates.sdf	Project Import	4 years ago
gates.v	Project Import	4 years ago
rng_haltonBase2.synth_yosys.v	for release 0.0.4	1 year ago
test_bench.py	for release 0.0.4	1 year ago
test_circuit.py	for release 0.0.4	1 year ago
test_logic.py	for release 0.0.4	1 year ago
test_logic_sim.py	for release 0.0.4	1 year ago
test_sdf.py	for release 0.0.4	1 year ago
test_stil.py	for release 0.0.4	1 year ago
test_verilog.py	for release 0.0.4	1 year ago
test_wave_sim.py	for release 0.0.4	1 year ago