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A python module for parsing, processing, and simulating gate-level circuits.
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Branch: devel
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kyupy/tests
Stefan Holst deb4599206
fix tests 		9 months ago
..
__init__.py Project Import 4 years ago
b01.bench Project Import 4 years ago
b01.v Project Import 4 years ago
b15_2ig.sa_nf.stil.gz new into demo 2 years ago
b15_2ig.sdf.gz new into demo 2 years ago
b15_2ig.tf_nf.stil.gz new into demo 2 years ago
b15_2ig.v.gz doc improvements 2 years ago
b15_4ig.sa_rf.stil.gz alap toposort, improve tests 1 year ago
b15_4ig.sdf.gz doc improvements 2 years ago
b15_4ig.v.gz doc improvements 2 years ago
conftest.py mux21 in 6v logic sim, more test fixtures 9 months ago
gates.sdf cond in sdf parser. ignored for now. 1 year ago
gates.v cond in sdf parser. ignored for now. 1 year ago
rng_haltonBase2.synth_yosys.v better docs, new techlib as default, fix tests 1 year ago
test_bench.py interface -> io_nodes, io_loc fix 2 years ago
test_circuit.py types, perf op growing list, keep s_nodes 1 year ago
test_logic.py support more cells in logic sim 2 years ago
test_logic_sim.py mux21 in 6v logic sim, more test fixtures 9 months ago
test_sdf.py cond in sdf parser. ignored for now. 1 year ago
test_stil.py better docs, new techlib as default, fix tests 1 year ago
test_verilog.py cond in sdf parser. ignored for now. 1 year ago
test_wave_sim.py fix tests 9 months ago