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A python module for parsing, processing, and simulating gate-level circuits.
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Branch: devel
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kyupy/tests
Stefan Holst 09420fd72c
new logic sim interface prototype, simprim lib and test 		1 day ago
..
__init__.py Project Import 5 years ago
all_kyupy_simprims.minimal.v new logic sim interface prototype, simprim lib and test 1 day ago
all_kyupy_simprims.v new logic sim interface prototype, simprim lib and test 1 day ago
b01.bench Project Import 5 years ago
b01.v Project Import 5 years ago
b15_2ig.sa_nf.stil.gz new into demo 2 years ago
b15_2ig.sdf.gz new into demo 2 years ago
b15_2ig.tf_nf.stil.gz new into demo 2 years ago
b15_2ig.v.gz doc improvements 2 years ago
b15_4ig.sa_rf.stil.gz alap toposort, improve tests 2 years ago
b15_4ig.sdf.gz doc improvements 2 years ago
b15_4ig.v.gz doc improvements 2 years ago
conftest.py mux21 in 6v logic sim, more test fixtures 2 years ago
gates.sdf cond in sdf parser. ignored for now. 2 years ago
gates.v cond in sdf parser. ignored for now. 2 years ago
kyupy_simprims.genlib new logic sim interface prototype, simprim lib and test 1 day ago
map_to_minimal.abc new logic sim interface prototype, simprim lib and test 1 day ago
minimal.genlib new logic sim interface prototype, simprim lib and test 1 day ago
rng_haltonBase2.synth_yosys.v better docs, new techlib as default, fix tests 2 years ago
test_bench.py interface -> io_nodes, io_loc fix 3 years ago
test_circuit.py euivalence test, op format doc 3 days ago
test_logic.py support more cells in logic sim 2 years ago
test_logic_sim.py new logic sim interface prototype, simprim lib and test 1 day ago
test_sdf.py cond in sdf parser. ignored for now. 2 years ago
test_stil.py better docs, new techlib as default, fix tests 2 years ago
test_verilog.py cond in sdf parser. ignored for now. 2 years ago
test_wave_sim.py fault injection for 4v sim, wave_sim test fix 2 weeks ago