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2 Commits

Author SHA1 Message Date
Stefan Holst 4bb3f3424a cond in sdf parser. ignored for now. 1 year ago
Stefan Holst a6243b43f6 keep s_nodes 1 year ago
  1. 2
      src/kyupy/circuit.py
  2. 9
      src/kyupy/sdf.py
  3. 39
      tests/gates.sdf
  4. 12
      tests/gates.v
  5. 6
      tests/test_sdf.py
  6. 12
      tests/test_verilog.py

2
src/kyupy/circuit.py

@ -459,7 +459,7 @@ class Circuit: @@ -459,7 +459,7 @@ class Circuit:
for l, ll in zip(impl_out_lines, node_out_lines): # connect outputs
if ll is None:
if l.driver in node_map:
self.remove_dangling_nodes(node_map[l.driver], keep=set(self.s_nodes))
self.remove_dangling_nodes(node_map[l.driver], keep=ios)
continue
if len(l.reader.outs) > 0: # output is also read by impl. circuit, connect to fork.
ll.driver = node_map[l.reader]

9
src/kyupy/sdf.py

@ -156,6 +156,10 @@ class SdfTransformer(Transformer): @@ -156,6 +156,10 @@ class SdfTransformer(Transformer):
entries = [e for a in args if hasattr(a, 'children') for e in a.children]
return name, entries
@staticmethod
def cond(args): # ignore conditions
return args[1]
@staticmethod
def start(args):
name = next((a for a in args if isinstance(a, str)), None)
@ -180,9 +184,12 @@ GRAMMAR = r""" @@ -180,9 +184,12 @@ GRAMMAR = r"""
| "(INSTANCE" ID? ")"
| "(TIMINGCHECK" _ignore* ")"
| delay )* ")"
delay: "(DELAY" "(ABSOLUTE" (interconnect | iopath)* ")" ")"
delay: "(DELAY" "(ABSOLUTE" (interconnect | iopath | cond)* ")" ")"
interconnect: "(INTERCONNECT" ID ID triple* ")"
iopath: "(IOPATH" ID_OR_EDGE ID_OR_EDGE triple* ")"
cond: "(" "COND" cond_port_expr iopath ")"
?cond_port_expr: ID | "(" cond_port_expr ")" | cond_port_expr BINARY_OP cond_port_expr
BINARY_OP: /&&/ | /==/
NAME: /[^"]+/
ID_OR_EDGE: ( /[^() ]+/ | "(" /[^)]+/ ")" )
ID: ( /[^"() ]+/ | "\"" /[^"]+/ "\"" )

39
tests/gates.sdf

@ -7,22 +7,49 @@ @@ -7,22 +7,49 @@
(TEMPERATURE 25.00:25.00:25.00)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "NAND2X1")
(CELLTYPE "NAND2_X1")
(INSTANCE nandgate)
(DELAY
(ABSOLUTE
(IOPATH IN1 QN (0.099:0.103:0.103) (0.122:0.127:0.127))
(IOPATH IN2 QN (0.083:0.086:0.086) (0.100:0.104:0.104))
(IOPATH A1 ZN (0.099:0.103:0.103) (0.122:0.127:0.127))
(IOPATH A2 ZN (0.083:0.086:0.086) (0.100:0.104:0.104))
)
)
)
(CELL
(CELLTYPE "AND2X1")
(CELLTYPE "AND2_X1")
(INSTANCE andgate)
(DELAY
(ABSOLUTE
(IOPATH IN1 Q (0.367:0.378:0.378) (0.351:0.377:0.377))
(IOPATH IN2 Q (0.366:0.375:0.375) (0.359:0.370:0.370))
(IOPATH A1 ZN (0.367:0.378:0.378) (0.351:0.377:0.377))
(IOPATH A2 ZN (0.366:0.375:0.375) (0.359:0.370:0.370))
)
)
)
(CELL
(CELLTYPE "OAI21_X1")
(INSTANCE oai21gate)
(DELAY
(ABSOLUTE
(IOPATH B1 ZN (0.000:0.025:0.025) (0.000:0.013:0.013))
(IOPATH B2 ZN (0.000:0.030:0.030) (0.000:0.016:0.016))
( COND (B1 == 1'b0) && (B2 == 1'b1) (IOPATH A ZN (0.000:0.018:0.018)))
(COND (B1 == 1'b1) && (B2 == 1'b0) (IOPATH A ZN (0.000:0.018:0.018) (0.000:0.016:0.016)))
(COND (B1 == 1'b1) && (B2 == 1'b1) (IOPATH A ZN (0.000:0.019:0.019) (0.000:0.014:0.014)))
)
)
)
(CELL
(CELLTYPE "MUX2_X1")
(INSTANCE mux2gate)
(DELAY
(ABSOLUTE
(COND (B == 1'b0) && (S == 1'b0) (IOPATH A Z (0.000:0.037:0.037) (0.000:0.058:0.058)))
(COND (B == 1'b1) && (S == 1'b0) (IOPATH A Z (0.000:0.037:0.037) (0.000:0.058:0.058)))
(COND (A == 1'b0) && (S == 1'b1) (IOPATH B Z (0.000:0.035:0.035) (0.000:0.056:0.056)))
(COND (A == 1'b1) && (S == 1'b1) (IOPATH B Z (0.000:0.035:0.035) (0.000:0.056:0.056)))
(COND (A == 1'b0) && (B == 1'b1) (IOPATH S Z (0.000:0.047:0.047) (0.000:0.073:0.073)))
(COND (A == 1'b1) && (B == 1'b0) (IOPATH S Z (0.000:0.072:0.072) (0.000:0.064:0.064)))
)
)
)

12
tests/gates.v

@ -1,11 +1,15 @@ @@ -1,11 +1,15 @@
module gates (a, b, o0, o1 );
module gates (a, b, c, o0, o1, o2, o3 );
input a;
input b;
input c;
output o0;
output o1;
output o2;
output o3;
AND2X1 andgate (.IN1 ( a ) , .IN2 ( b ) , .Q ( o0 ) ) ;
NAND2X1 nandgate (.IN1 ( a ) , .IN2 ( b ) , .QN ( o1 ) ) ;
AND2_X1 andgate (.A1 ( a ) , .A2 ( b ) , .ZN ( o0 ) ) ;
NAND2_X1 nandgate (.A1 ( a ) , .A2 ( b ) , .ZN ( o1 ) ) ;
OAI21_X1 oai21gate (.B1(a), .B2(b), .A(c), .ZN(o2) ) ;
MUX2_X1 mux2gate (.A(a), .B(b), .S(c), .Z(o3)) ;
endmodule

6
tests/test_sdf.py

@ -2,7 +2,7 @@ import numpy as np @@ -2,7 +2,7 @@ import numpy as np
from kyupy import sdf, verilog, bench
from kyupy.wave_sim import WaveSim, TMAX, TMIN
from kyupy.techlib import SAED32, SAED90
from kyupy.techlib import SAED32, NANGATE45
def test_parse():
test = '''
@ -80,9 +80,9 @@ def test_b15(mydir): @@ -80,9 +80,9 @@ def test_b15(mydir):
def test_gates(mydir):
c = verilog.load(mydir / 'gates.v', tlib=SAED90)
c = verilog.load(mydir / 'gates.v', tlib=NANGATE45)
df = sdf.load(mydir / 'gates.sdf')
lt = df.iopaths(c, tlib=SAED90)[1]
lt = df.iopaths(c, tlib=NANGATE45)[1]
nand_a = c.cells['nandgate'].ins[0]
nand_b = c.cells['nandgate'].ins[1]
and_a = c.cells['andgate'].ins[0]

12
tests/test_verilog.py

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
from kyupy import verilog
from kyupy.techlib import SAED90, SAED32
from kyupy.techlib import SAED90, SAED32, NANGATE45
def test_b01(mydir):
with open(mydir / 'b01.v', 'r') as f:
@ -26,12 +26,12 @@ def test_b15(mydir): @@ -26,12 +26,12 @@ def test_b15(mydir):
def test_gates(mydir):
c = verilog.load(mydir / 'gates.v', tlib=SAED90)
assert len(c.nodes) == 10
assert len(c.lines) == 10
c = verilog.load(mydir / 'gates.v', tlib=NANGATE45)
assert len(c.nodes) == 18
assert len(c.lines) == 21
stats = c.stats
assert stats['input'] == 2
assert stats['output'] == 2
assert stats['input'] == 3
assert stats['output'] == 4
assert stats['__seq__'] == 0

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