Tag: v0.0.6

devel

main

v0.0.1

v0.0.2

v0.0.3

v0.0.4

v0.0.5

v0.0.6

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from 'v0.0.6'

${ noResults }

Commit Graph

3 Commits (v0.0.6)

Author	SHA1	Message	Date
Stefan Holst	3193df726f	need 3.12 for generic types	3 weeks ago
Stefan Holst	d247115744	for release 0.0.6 ... - sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API) - sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic - Circuit: dot output fix and better style, fixed equivalence check of lines and nodes. - Techlib: Added KYUPY library with supported simulation primitives for debug and testing - tests: fixed and added more for better coverage - more type annotations - updated project config and dependencies for better uv experience, newer lark, newer numpy	3 weeks ago
Stefan Holst	aea633ac8d	for release 0.0.5 ... * Techlib: fix NanGate variants * Circuit: more visitor and manipulator utilities * mv_transition: produce stable values when arguments are UNASSIGNED * Verilog: better assign processing * STIL parsing improvements * SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching * sim: use ALAP topo-sort * logic_sim: improved fault injection, faster 6V sim * wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor * log: fix limiter	6 months ago