kyupy

223 Commits

2 Branches

6 Tags

61 MiB

Tree: f66953f2d3

Commit Graph

Author	SHA1	Message	Date
Stefan Holst	351d809306	for release 0.0.4 - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements	3 years ago
stefan	63c0b48537	bump	3 years ago
Stefan Holst	08a22cf251	move sources to src, add package info and release 0.0.1	6 years ago

Author

SHA1

Message

Date

Stefan Holst

351d809306

for release 0.0.4

- Circuit: is now pickleable and comparable
- Circuit: utilities for locating/indexing io-ports
- Verilog: parser fixes, support yosys-style verilog
- SDF: parser fixes, full XOR support
- STIL: parser fixes
- Simulators: faster, up to 4-input cells, pickleable
- WaveSim: WSA calculation support
- WaveSim: Per-simulation parameters and delays
- Logic: Data are now raw numpy arrays
- Logic: More tools for bit-packing
- Added DEF parser
- Better techlib support for NanGate, SAED, GSC180
- Tests and docs improvements

3 years ago

stefan

63c0b48537

bump

3 years ago

Stefan Holst

08a22cf251

move sources to src, add package info and release 0.0.1

6 years ago

2 Commits (f66953f2d3c9de6b46216f8e8fc3cd69ce12552e)