stefan
e8a9025c56
fix dot graph construction
1 week ago
stefan
8aa0f09254
logic_sim: better docs, deprecate LogicSim, move tests to newer classes
1 week ago
stefan
4f7e605819
use tlib functions to identify ffs and latches
1 week ago
stefan
c1ea05555e
fix verilog tests
1 week ago
stefan
e7b5567d87
let SimOps refuse building broken sim models.
1 week ago
stefan
3a2cfb7788
techlib decides on cell type comb/dff/latch
2 weeks ago
Nosaka Naoya
ca25942b27
better type annotation, always return list
2 weeks ago
Nosaka Naoya
f863b70457
use float32 for delays, more robust node-port name splitting
1 month ago
stefan
bd23dfb016
get a techlib by name
1 month ago
stefan
d3d06722c1
faster mv xor and new merge fct
1 month ago
stefan
1f984c9bd9
faster fanout generator function
1 month ago
stefan
0c8a2b7746
add return type
2 months ago
stefan
f66953f2d3
fix sim model gen for undriven outputs
2 months ago
stefan
7203145a1d
better docs and repr
2 months ago
stefan
32e0766d41
s_len param for vcd
2 months ago
stefan
9570161744
fix half adder
2 months ago
stefan
a594e2fb9a
annotation and repr
2 months ago
stefan
1bc9dc0e9d
bench parsing docs
2 months ago
Nosaka Naoya
c5bdeb4a68
add type annotation
2 months ago
Nosaka Naoya
67db64611b
fix cuda launch expecting pure ints for grid spec
2 months ago
stefan
7a9ed1e536
vcd improvements
2 months ago
stefan
fcd9b78c24
rm test.py
2 months ago
stefan
f975765bbb
first version of a vcd parser
2 months ago
stefan
3cb1b2bc86
first version of a vcd parser
2 months ago
stefan
c4aecbd6c9
skywater 130nm tech library
2 months ago
stefan
25ff1fb2dc
fixups for empty standard cells
2 months ago
Nosaka Naoya
f0b55eed27
version bump
7 months ago
Nosaka Naoya
3700ae9b33
need 3.12 for generic types
7 months ago
Nosaka Naoya
df695e0aa1
for release 0.0.6
...
- sim: added LogicSim2V, LogicSim4V, LogicSim6V (faster and simpler API)
- sim: fixed model for: many-input gates in bench; dangling nodes; POs that drive further logic
- Circuit: dot output fix and better style, fixed equivalence check of lines and nodes.
- Techlib: Added KYUPY library with supported simulation primitives for debug and testing
- tests: fixed and added more for better coverage
- more type annotations
- updated project config and dependencies for better uv experience, newer lark, newer numpy
7 months ago
Nosaka Naoya
a28128830d
beginning simple always block parsing in verilog
7 months ago
Stefan Holst
20cf441abb
add doc gen dependencies
7 months ago
Nosaka Naoya
5ac21edbb1
migrate readme to markdown
7 months ago
Nosaka Naoya
f0d74777af
add dff to techlib
7 months ago
Nosaka Naoya
3848665533
ignore more generated python files
7 months ago
Nosaka Naoya
541cccd756
fix sim model for PO that also drive further logic
7 months ago
Stefan Holst
fed66f85cb
fix oob in test
7 months ago
Stefan Holst
2eb10f83b0
add pytest dev dependency
7 months ago
Nosaka Naoya
dd4e5c861a
fix sim model generation for circuits with dangling nodes
7 months ago
Nosaka Naoya
9cebbcce8f
support for storing responses separately
8 months ago
stefan
31434cfd51
4v sim, fixed 6v sim, better testing
8 months ago
stefan
ce94210b52
adding more types
8 months ago
Nosaka Naoya
09420fd72c
new logic sim interface prototype, simprim lib and test
8 months ago
Nosaka Naoya
5bcc1c1d77
new synthetic techlib with kyupy simprims
8 months ago
Nosaka Naoya
df8a58f57b
generate proper simprims in bench parser
8 months ago
Nosaka Naoya
3dfd0cb60d
euivalence test, op format doc
8 months ago
Nosaka Naoya
21439e3595
circuit objects and nodes/lines of different circuits are not quivalent.
8 months ago
Nosaka Naoya
88a5c79161
dot fix and updated intro nb
8 months ago
Nosaka Naoya
9ca437fe47
fault injection for 4v sim, wave_sim test fix
8 months ago
Nosaka Naoya
0cdaf71963
fix for latest lark
8 months ago
Nosaka Naoya
75972d7bb2
numba config deprecated
8 months ago