Tree: c4aecbd6c9

devel

main

v0.0.1

v0.0.2

v0.0.3

v0.0.4

v0.0.5

v0.0.6

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from 'c4aecbd6c9'

${ noResults }

Commit Graph

7 Commits (c4aecbd6c94e86a18a3a7faab14789e84af61280)

Author	SHA1	Message	Date
Stefan Holst	aea633ac8d	for release 0.0.5 ... * Techlib: fix NanGate variants * Circuit: more visitor and manipulator utilities * mv_transition: produce stable values when arguments are UNASSIGNED * Verilog: better assign processing * STIL parsing improvements * SDF: conditional parsing (semantics ignored for now), better interconnect annotation, more robust name matching * sim: use ALAP topo-sort * logic_sim: improved fault injection, faster 6V sim * wave_sim: use correct thresholds for pulse filtering, partial delta-sim support, per-sim delay factor * log: fix limiter	11 months ago
Stefan Holst	a4b7364478	mux21 in 6v logic sim, more test fixtures	2 years ago
Stefan Holst	a6d1e4099c	alap toposort, improve tests	3 years ago
Stefan Holst	351d809306	for release 0.0.4 ... - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements	3 years ago
Stefan Holst	35e727e714	better docs, new techlib as default, fix tests	3 years ago
Stefan Holst	cf9a98b5ce	del deprecated sdf code, explicit tlib use	3 years ago
Stefan Holst	44b0c887d7	random sampling of delays	3 years ago
Stefan Holst	3497bfdc75	first gpu-code, cached test fixtures	3 years ago
Stefan Holst	0c5a7f56e1	Project Import	6 years ago