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244 Commits (7a69ce901680164ad392a303f11b9f8067df5728)
 

Author SHA1 Message Date
stefan 7a69ce9016 sort times
1 day ago
stefan f5af7ec3d9 typing and docs for interpret, mvarray
2 days ago
stefan 53309f9e59 simple incremental sim using dirty flags
3 days ago
stefan c90bc89522 construct input connected to output on passthrough connection
4 days ago
stefan bda89dc1b0 support for simple text-based pattern format
4 days ago
stefan 449bf9a031 more flexible progress logging
1 week ago
stefan df463826ae fix ffr
1 week ago
stefan aebdf9540d pin_name type annotations
1 week ago
stefan 9dc58f8c40 dev deps
1 week ago
stefan e8a9025c56 fix dot graph construction
1 week ago
stefan 8aa0f09254 logic_sim: better docs, deprecate LogicSim, move tests to newer classes
1 week ago
stefan 4f7e605819 use tlib functions to identify ffs and latches
1 week ago
stefan c1ea05555e fix verilog tests
1 week ago
stefan e7b5567d87 let SimOps refuse building broken sim models.
1 week ago
stefan 3a2cfb7788 techlib decides on cell type comb/dff/latch
2 weeks ago
Nosaka Naoya ca25942b27 better type annotation, always return list
2 weeks ago
Nosaka Naoya f863b70457 use float32 for delays, more robust node-port name splitting
1 month ago
stefan bd23dfb016 get a techlib by name
1 month ago
stefan d3d06722c1 faster mv xor and new merge fct
1 month ago
stefan 1f984c9bd9 faster fanout generator function
1 month ago
stefan 0c8a2b7746 add return type
2 months ago
stefan f66953f2d3 fix sim model gen for undriven outputs
2 months ago
stefan 7203145a1d better docs and repr
2 months ago
stefan 32e0766d41 s_len param for vcd
2 months ago
stefan 9570161744 fix half adder
2 months ago
stefan a594e2fb9a annotation and repr
2 months ago
stefan 1bc9dc0e9d bench parsing docs
2 months ago
Nosaka Naoya c5bdeb4a68 add type annotation
2 months ago
Nosaka Naoya 67db64611b fix cuda launch expecting pure ints for grid spec
2 months ago
stefan 7a9ed1e536 vcd improvements
2 months ago
stefan fcd9b78c24 rm test.py
2 months ago
stefan f975765bbb first version of a vcd parser
2 months ago
stefan 3cb1b2bc86 first version of a vcd parser
2 months ago
stefan c4aecbd6c9 skywater 130nm tech library
2 months ago
stefan 25ff1fb2dc fixups for empty standard cells
2 months ago
Nosaka Naoya f0b55eed27 version bump
7 months ago
Nosaka Naoya 3700ae9b33 need 3.12 for generic types
7 months ago
Nosaka Naoya df695e0aa1 for release 0.0.6
7 months ago
Nosaka Naoya a28128830d beginning simple always block parsing in verilog
7 months ago
Stefan Holst 20cf441abb add doc gen dependencies
7 months ago
Nosaka Naoya 5ac21edbb1 migrate readme to markdown
7 months ago
Nosaka Naoya f0d74777af add dff to techlib
7 months ago
Nosaka Naoya 3848665533 ignore more generated python files
7 months ago
Nosaka Naoya 541cccd756 fix sim model for PO that also drive further logic
7 months ago
Stefan Holst fed66f85cb fix oob in test
7 months ago
Stefan Holst 2eb10f83b0 add pytest dev dependency
7 months ago
Nosaka Naoya dd4e5c861a fix sim model generation for circuits with dangling nodes
7 months ago
Nosaka Naoya 9cebbcce8f support for storing responses separately
8 months ago
stefan 31434cfd51 4v sim, fixed 6v sim, better testing
8 months ago
stefan ce94210b52 adding more types
8 months ago