Tree: 5bcc1c1d77

devel

main

v0.0.1

v0.0.2

v0.0.3

v0.0.4

v0.0.5

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from '5bcc1c1d77'

${ noResults }

Commit Graph

2 Commits (5bcc1c1d77bea3c0a58516a9458a3c1f56a63f4b)

Author	SHA1	Message	Date
Stefan Holst	351d809306	for release 0.0.4 ... - Circuit: is now pickleable and comparable - Circuit: utilities for locating/indexing io-ports - Verilog: parser fixes, support yosys-style verilog - SDF: parser fixes, full XOR support - STIL: parser fixes - Simulators: faster, up to 4-input cells, pickleable - WaveSim: WSA calculation support - WaveSim: Per-simulation parameters and delays - Logic: Data are now raw numpy arrays - Logic: More tools for bit-packing - Added DEF parser - Better techlib support for NanGate, SAED, GSC180 - Tests and docs improvements	2 years ago
Stefan Holst	0968cb451e	docs, fix stil unassigned, fix io_locs for busses	2 years ago
Stefan Holst	64e1de396f	New m-valued logic arrays, documentation, 0.0.2 ... - MVArray for multi-valued logic - BPArray for bit-parallel storage layout - Started documenting with Sphinx - Migrated simulators to new BPArray	5 years ago
Stefan Holst	cff18e0915	start documentation	5 years ago